Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block

ABSTRACT

In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

This is a continuation of application Ser. No. 240,450, filed Sept. 2, 1988, which is a continuation of application Ser. No. 102,245, filed Sept. 28, 1987, now abandoned, which is a continuation of application Ser. No. 008,467, filed Jan. 29, 1987, now abandoned, which is a continuation of application Ser. No. 575,567, filed Jan. 31, 1984, now U.S. Pat. No. 4,689,503.

BACKGROUND OF THE INVENTION

The present invention relates to a technique which is effective when applied to semiconductor integrated circuits, for example, a logic semiconductor integrated circuit whose input and output levels are TTL levels and whose internal logic levels are CMOS levels.

FIG. 1 shows a block diagram of a logic semiconductor integrated circuit IC having TTL levels as its input and output levels and CMOS levels as its internal logic levels, which circuit was studied by the inventors before the present invention.

Such circuit IC includes an input buffer 10 for level-converting input signals of TTL levels IN₁, IN₂, . . . IN_(n) into signals of CMOS levels, an internal logic block 11 for executing logic opertions with the CMOS levels, and an output buffer 12 for level-converting the CMOS level output signals of the internal logic block 11 into output signals of TTL levels OUT₁, OUT₂, . . . OUT_(m). The respective circuits 10, 11 and 12 are fed with a supply voltage V_(CC) of 5 volts, and are properly grounded.

A high level input voltage V_(iH10) to be supplied to the input terminals IN₁, IN₂, . . . IN_(n) of the input buffer 10 is set at 2.0 volts or above, while a low level input voltage V_(iL10) is set at 0.8 volt or below. Accordingly, an input threshold voltage V_(ith10) concerning the input terminals IN₁, IN₂, . . . IN_(n) of the input buffer 10 is set at 1.3-1.5 volt which is between 0.8 volt and 2.0 volts.

On the other hand, a high level output voltage V_(oH10) to be derived from the output of the input buffer 10 is set to be equal to the high level input voltage V_(iH11) of the internal logic block 11, while a low level output voltage V_(oL10) to be derived from the output of the input buffer 10 is set to be equal to the low level input voltage V_(iL11) of the internal logic block 11. Accordingly, letting V_(TP) and V_(TN) denote the threshold voltages of a P-channel MOS FET and an N-channel MOS FET which constitute a CMOS inverter in the internal logic block 11, respectively, and V_(CC) denote the supply voltage, the above voltages V_(oH10), V_(iH11), V_(oL10) and V_(iL11) are respectively set as follows:

    V.sub.oH10 =V.sub.iH11 >V.sub.CC -|V.sub.TP |(1)

    V.sub.oL10 =V.sub.iL11 <V.sub.TN                           ( 2)

When V_(CC) is set at 5 volts, |V_(TP) |at 0.6 volt and V_(TN) at 0.6 volt, V_(oH10) and V_(iH11) are set at above 4.4 volts, and V_(oL10) and V_(iL11) at below 0.6 volt.

Accordingly, the input logic threshold voltage V_(ith11) of the CMOS inverter in the internal logic block 11 is set at approximately 2.5 volts which is between 0.6 volt and 4.4 volts.

Likewise, the high level output voltage V_(oH11) of the internal logic block 11 and the high level input voltage V_(iH12) of the output buffer 12 are set at above 4.4 volts, the low level output voltage V_(oL11) of the internal logic block 11 and the low level input voltage V_(iL12) of the output buffer 12 are set at below 0.6 volt, and the input logic threshold voltage V_(ith12) of the output buffer 12 is set at approximately 2.5 volts which is between 0.6 volt and 4.4 volts.

In order to generate the output signals of TTL levels, the output buffer 12 has its high level output voltage V_(oH12) set at 2.7 volts or above and its low level output voltage V_(oL12) at 0.5 volt or below.

FIG. 2 is a circuit diagram showing one input buffer 10 which was constructed and studied by the inventors for test purposes before the present invention, and which is constructed of P-channel MOS FETs M_(p1), M_(p2), N-channel MOS FETs M_(n1), M_(n2), M_(n3) and a resistor R_(p). The gates, sources and drains of the MOS FETs are respectively indicated by symbols g, s and d.

A first stage CMOS inverter composed of the FETs M_(p1) and M_(n1), and a second stage CMOS inverter composed of the FETs M_(p2) and M_(n2) are connected in cascade. The components R_(p) and M_(n3) constitute a gate protection circuit for protecting the gate insulating films of the FETs M_(p1) and M_(n1). An output capacitance C_(s) connected to the drains of the FETs M_(p2) and M_(n2) of the second stage CMOS inverter has, in actuality, its value determined by the drain capacitances of the FETs M_(p2) and M_(n2), the wiring stray capacitance between the output of the input buffer 10 and the input of the internal logic block 11, and the input capacitance of the internal logic block 11.

The ratios W/L between the channel widths W and channel lengths L of the MOS FETs M_(p1), M_(p2), M_(n1), M_(n2) and M_(n3) are respectively set at 27/3.5, 42/3, 126/3.5, 42/3 and 15/3. The resistor R_(p) is set at a resistance of 2 kiloohms.

FIG. 3 illustrates the dependencies of the propagation delay times t_(pHL), t_(pLH) of the input buffer 10 of FIG. 2 upon the output capacitance C_(s). In the figure, the axis of ordinates represents the propagation delay times, while the axis of abscissas represents the output capacitance C_(s). FIG. 3 also shows delay time dependencies for the buffers of FIGS. 14, 19, 22 and 31, as will be discussed in detail later.

A definition of the propagation delay times used in FIG. 3 and throughout this specification is shown in FIG. 35. As illustrated in FIG. 35, the first propagation delay time t_(pHL) is defined as a period of time which elapses from the time that an input INPUT to the buffer reaches its 50% value until the time an output OUTPUT from the buffer changing from a high level to a low level reaches its 50% value. The second propagation delay time t_(pHL) is defined as a period of time which elapses from the time the input INPUT to the buffer reaches its 50% value until the time when output OUTPUT from the buffer changing from the low level to the high level reaches its 50% value. In FIG. 35, t_(f) is defined as a fall time, and t_(r) as a rise time between the 10% and 90% values of the output of the buffer.

Thus, as understood from FIG. 3, the output capacitance-dependency K_(HL) (=Δt_(pHL) /ΔC_(s)) of the first propagation delay time t_(pHL) of the input buffer 10 in FIG. 2 is about 0.8 nsec/pF, and the output capacitance-dependency K_(LH) (=Δt_(pLH) /ΔC_(s)) of the second propagation delay time t_(pLH) is about 1.4 nsec/pF. Both of these values are relatively large.

In the input buffer 10 of FIG. 2, in order to set the input threshold voltage V_(ith10) at approximately 1.3-1.5 volt, the ratios W/L between the channel widths and channel lengths of the FETs M_(p1) and M_(n1) of the first stage CMOS inverter are made greatly different, and in order to lessen the output capacitance-dependencies K_(HL) and K_(LH) of the respective propagation delay times t_(pHL) and t_(pLH), both the ratios W/L of the FETs M₂ and M_(n2) of the second stage CMOS inverter are set at the large value of 42/3 so as to increase the channel conductances of these FETs M_(p2) and M_(n2).

To the end of reducing both the output capacitance-dependencies K_(HL) and K_(LH), the ratios W/L of the FETs M_(p2) and M_(n2) of the second stage CMOS inverter may be increased more and more. This, however, incurs a conspicuous increase in the occupation area of the input buffer 10 on the surface of an integrated circuit chip for the following reason, to form an obstacle to enhancement in the density of integration.

In the production technology of integrated circuits, fining is being vigorously promoted at present. With the present-day photolithography based on exposure to ultraviolet radiation, however, the channel length L of a MOS FET is often set with 3 μm as its practical lower limit value. In order to set the ratio W/L of the MOS FET at a very large value, therefore, the channel width W thereof must be set at an extraordinary large value. Eventually, the device area of the MOS FET increases conspicuously.

FIG. 4 is a circuit diagram showing one output buffer 12 which was constructed and studied by the inventors for test purposes before the present invention and which is constructed of a P-channel MOS FET M_(p4) and an N-channel MOS FET M_(n4). The gates, sources and drains of the MOS FETs are respectively indicated by symbols g, s and d.

In the integrated circuit IC, the output signal of CMOS level from the internal logic block 11 is applied to the gates of the FETs M_(p4) and M_(n4) of the output buffer 12. Terminal No. 30 is fed with the supply voltage V_(CC) of 5 volts. In order to set the input logic threshold voltage V_(ith12) of the output buffer 12 at approximately 2.5 volts, accordingly, the ratios W/L of the FETs M_(p4) and M_(n4) are set at values equal to each other.

FIG. 4 also shows a TTL circuit 14, which is fed with the supply voltage V_(CC) of 5 volts through terminal No. 35. The output signal of TTL level from the output buffer 12 is derived from terminal No. 20, and is supplied to one emitter of the multi-emitter transistor Q₁ of the TTL circuit 14 through terminal No. 32.

A variety of TTL circuits are presently known from publications in the art including a standard TTL circuit, a Schottky TTL circuit, a low power Schottky TTL circuit and an advanced low power Schottky TTL circuit. Naturally, the characteristics of these circuits are somewhat different from one another.

The output of the output buffer 12 needs to drive a large number of inputs of the TTL circuit 14 at the same time and in parallel. A criterion for the drive ability is to be capable of driving 20 inputs of a low power Schottky TTL circuit in parallel.

When the output of the output buffer 12 is at its low level, a low level input current I_(IL) of 0.4 mA flows from one input of the low power Schottky TTL circuit into the drain-source path of the N-channel MOS FET M_(n4) of the output buffer 12. Accordingly, the FET M_(n4) needs to pour a total of 8 mA in order that the output buffer 12 may drive the aforementioned 20 inputs to the low level.

On the other hand, the low level output voltage V_(oL12) of the output buffer 12 must be 0.5 volt or below as already explained. Therefore, the ON-resistance R_(ON) of the N-channel MOS FET M_(n4) of the output buffer 12 must be set at a small value of 0.5 volt/8 milliampere =62.5 ohms or so.

In order to make the ON-resistance R_(ON) of the FET M_(n4) such a low resistance, the ratio W/L of the FET M_(n4) must be set at a very large value of 700/3 to 1000/3. Meanwhile, as stated above, both the ratios W/L of the FETs M_(p4) and M_(n4) need to be equal values for the purpose of setting the input logic threshold voltage V_(ith12) of the output buffer 12 at approximately 2.5 volts. Therefore, also the ratio W/L of the P-channel MOS FET M_(p4) of the output buffer 12 must be set at the very large value of 700/3 to 1000/3.

This fact similarly brings about a conspicuous increase in the occupation area of the output buffer 12 on the surface of the integrated circuit chip, to hamper enhancement in the density of integration. Moreover, it incurs drastic lowering in the switching speed of the internal logic block 11 for the following reason.

When both the ratios W/L of the two MOS FETs M_(p4) and M_(n4) of the output buffer 12 are set at the large values noted above, the gate capacitances of these MOS FETs become large values proportionally. Since the gate capacitances of the FETs M_(p4) and M_(n4) constitute the output load capacitance of the internal logic block 11, these gate capacitances and the output resistance of the internal logic block 11 incur the lowering of the switching speed of the internal logic block 11.

Meanwhile, since the output of the output buffer 12 is not only derived from the external output terminal (terminal No. 20) of the integrated circuit IC, but also connected to the large number of input terminals of the TTL circuit 14 through external wiring, the output load capacitance C_(x) of the output buffer 12 often becomes a very large value.

FIG. 5 illustrates the dependencies of the propagation delay times t_(pHL), t_(pLH) upon the output load capacitance C_(x) of the output buffer 12 in FIG. 4. In the graph of FIG. 5, the axis of ordinates represents the propagation delay times, while the axis of abscissas represents the output load capacitance. FIG. 5 also shows such delay time dependencies for FIG. 34, as will be discussed later.

Thus, as understood from FIG. 5, the capacitance-dependency K_(HL) (=Δt_(pHL) /ΔC_(x)) of the first propagation delay time t_(pHL) of the output buffer 12 in FIG. 4 is about 0.3 nsec/pF, and the capacitance-dependency K_(LH) (=Δt_(pLH) /ΔC_(x)) of the second propagation delay time t_(pLH) is about 0.17 nsec/pF. Both of these are undesirably large.

Accordingly, the input buffer 10 of FIG. 2 which the inventors tested in development of the present invention involves problems as summed up below.

(1) In order to lessen the output capacitance-dependencies of the propagation delay times of the input buffer 10, the ratios W/L of both the MOS FETs M_(p2) and M_(n2) of the second stage CMOS inverter of the input buffer 10 must be made large, which hampers enhancement in the density of integration. Particularly in a case where the integrated circuit IC is of the master slice type or the semi-custom gate array type, there is the possibility that a very large number of gate input terminals in the internal logic block 11 will be connected to the output of the input buffer 10. When the output capacitance C_(s) of the input buffer 10 accordingly becomes very great, the above problem is very serious.

(2) Further, the first stage of the input buffer 10 is formed of the CMOS inverter M_(p1), M_(n1). Therefore, even when the gate protection circuit composed of the elements R_(p) and M_(n3) is connected, the breakdown strengths of the gate insulating films of both the MOS FETs M_(p1), M_(n1) against a surge voltage applied to the input terminal IN₁ are not satisfactory.

In addition, the output buffer 12 of FIG. 4 which the inventors tested in the development of the present invention involves problems as summed up below.

(3) In order to set the input logic threshold voltage V_(ith12) of the output buffer 12 at approximately 2.5 volts and to enhance the current sink ability at the low level output of the output buffer 12, the ratios W/L of both the MOS FETs M_(p4) and M_(n4) must be set at large values equal to each other, which hampers enhancement in the density of integration.

(4) When the ratios W/L of both the MOS FETs M_(p4) and M_(n4) of the output buffer 12 are made large, the gate capacitances of these MOS FETs also increase. In consequence, these gate capacitances and the output resistance of the internal logic block 11 incur lowering in the switching speed of the internal logic block 11. Particularly in a case where the output stage of the internal logic block 11 is composed of MOS FETs of high output resistance, the lowering of the switching speed is conspicuously problematic.

(5) Since the output buffer 12 is composed of the MOS FETs M_(p4) and M_(n4), the dependencies of the propagation delay times upon the output load capacitance C_(x) are great. Particularly in a case where a large number of input terminals of the TTL circuit 14 are connected to the output of the output buffer 12, this problem becomes important.

SUMMARY OF THE INVENTION

The present invention concerns a semiconductor integrated circuit having an internal logic block for generating output signals of CMOS levels in response to input signals of CMOS levels applied thereto, an input buffer for level conversion such as TTL-CMOS level conversion for the internal logic block, and/or an output buffer for level conversion such as CMOS-TTL level conversion. In particular, the present invention has for its objects to permit enhancement in the density of integration and to lessen the output capacitance-dependency of the operating speed of the input buffer and/or the output buffer and enhance such operating speed.

The aforementioned and other objects of the present invention and novel features thereof will become apparent from the description of the specification as well as the accompanying drawings of the present invention.

Typical aspects of performance of the present invention will be briefly explained below.

In the level converter of a TTL-CMOS level conversion input buffer for an internal logic block which operates with CMOS levels, output transistors for executing the charge or discharge of the output capacitance of the level converter are formed of bipolar transistors, whereby the object of reducing the propagation delay time of the input buffer and the capacitance-dependency thereof can be accomplished owing to the function that, even when smaller in device size than a MOS FET, the bipolar transistor exhibits a lower output resistance and a higher current gain, so it can produce a great charging current or discharging current.

Further, in the level converter of a CMOS-TTL level conversion output buffer for an internal logic block which operates with CMOS levels, output transistors for executing the charge or discharge of the output load capacitance of the level converter are formed of bipolar transistors, whereby the object of reducing the propagation delay time of the output buffer and the capacitance-dependency thereof can be accomplished owing to the function that, even when smaller in device size than a MOS FET, the bipolar transistor exhibits a lower output resistance and a higher current gain, so it can produce a great charging current or discharging current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a logic semiconductor integrated circuit IC which was studied by the inventors before the present invention;

FIG. 2 shows a cicuit diagram of an input buffer which was studied by the inventors before the present invention;

FIG. 3 shows the output capacitance-dependencies of the propagation delay times of the input buffer in FIG. 2;

FIG. 4 shows a circuit diagram of an output buffer which was studied by the inventors before the present invention;

FIG. 5 shows the output load capacitance-dependencies of the propagation delay times of the output buffer in FIG. 4;

FIG. 6 shows a block diagram of a logic semiconductor integrated circuit according to an embodiment of the present invention;

FIGS. 7 and 8 show circuit examples of a CMOS·NAND gate 211 in the circuit of FIG. 6;

FIGS. 9 and 10 show circuit examples of a CMOS·NOR gate 21l in the circuit of FIG. 6;

FIGS. 11 and 12 show circuit examples of CMOS·R-S flip-flops within an internal logic block 21 in the circuit of FIG. 6;

FIG. 13 shows a circuit example of a CMOS gated R-S flip-flop within the internal logic block 21 in the circuit of FIG. 6;

FIGS. 14 to 31 show diagrams of various circuits of the level converter 201 of an input buffer 20 according to embodiments of the present invention;

FIGS. 32 to 34 and FIG. 36 show diagrams of various circuits of the level converter 221 of an output buffer 21 according to embodiments of the present invention;

FIG. 35 shows a diagram of input and output waveforms for defining first and second propagation delay times t_(pHL), t_(pLH) ;

FIG. 37 shows the layout of various circuit blocks on a semiconductor chip surface in a logic semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 38 shows a structural diagram illustrative of the state of connection of a semiconductor chip to the tab lead L_(T) of a lead frame L_(F) and connection of bonding wires in a logic semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 39 shows a diagram of the completion of a circuit according to an embodiment of the present invention after resin molding; and

FIG. 40 shows a block diagram of an electronic system constructed in such a way that a circuit according to an embodiment of the present invention and another circuit are packaged on a printed circuit board.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, embodiments of the present invention will be described referring to the drawings.

FIG. 6 shows a block diagram of a logic semiconductor integrated circuit IC according to an embodiment of the present invention. The integrated circuit includes a TTL-CMOS level conversion input buffer 20 which executes an operation similar to that of the input buffer 10 in FIG. 1, an internal logic block 21 which operates with CMOS levels similarly to the internal logic block 11 in FIG. 1, and a CMOS-TTL level conversion output buffer 22 which executes an operation similar to that of the output buffer 12 in FIG. 1. The respective circuits 20, 21 and 22 are fed with a supply voltage V_(CC) of 5 volts through terminal No. 30, and are properly grounded through terminal No. 31. The respective input and output high and low levels for the input buffer 20, the internal logic block 21 and the output buffer 22 are substantially the same as those respectively shown for the input buffer 10, the logic block 11 and the output buffer 12 in FIG. 1.

The input buffer 20 has a plurality of TTL-CMOS level converters 201, 202, . . . 20n, the respective inputs of which are connected to terminal No. 1, terminal No. 2, . . . terminal No. 19 and the respective outputs of which are connected with the internal logic block 21 by aluminum wiring layers inside the circuit IC.

The internal logic block 21 includes CMOS·NAND gates 211, 212, 213, 214, CMOS·NOR gates 21 (l-1), 21l, and if necessary, CMOS exclusive OR gates, CMOS transmission gates, CMOS inverters etc.

As shown in FIG. 7 by way of example, the CMOS·NAND gate 211 is constructed of a pure CMOS circuit which includes P-channel MOS FETs M₁, M₂ and N-channel MOS FETs M₃, M₄. Another example of the CMOS·NAND gate 211 can be constructed of a quasi-CMOS circuit which further includes N-P-N transistors Q₁, Q₂ and resistors R₁, R₂ as shown in FIG. 8. Since this quasi-CMOS circuit has its output stage composed of the bipolar transistors Q₁, Q₂, the output drive ability is enhanced, and the output load capacitance-dependency of the propagation delay time can be lessened.

As shown in FIG. 9 by way of example, the CMOS·NOR gate 21l is constructed of a pure CMOS circuit which includes P-channel MOS FETs M₁, M₂ and N-channel MOS FETs M₃, M₄. Another example of the CMOS·NOR gate 21l can be constructed of a quasi-CMOS circuit which further includes N-P-N transistors Q₁, Q₂ and resistors R₁, R₂ as shown in FIG. 10. Since this quasi-CMOS circuit has its output stage composed of the bipolar transistors Q₁, Q₂, the output drive ability is enhanced, and the output load capacitance-dependency of the propagation delay time can be lessened.

In the internal logic block 21, these CMOS·NAND gates and CMOS·NOR gates are connected in various forms in accordance with the master slice type or the semi-custom gate array type.

For example, an R-S flip-flop is constructed by combining two of the CMOS·NAND gates as shown in FIG. 11 or by combining two of the CMOS·NOR gates as shown in FIG. 12. Further, a gated R-S flip-flop which is controlled by a clock signal C is constructed by combining four of the CMOS·NOR gates as shown in FIG. 13.

In this manner, in the logic semiconductor integrated circuit IC of the master slice type or the gate array type conforming to the needs of users, the outputs of the level converters 201, 202, . . . 20n of the input buffer 20 and the inputs of the various gates or inverters of the internal logic block 21 are connected in various forms by altering only the wiring pattern thereof. Similarly, the outputs of the various gates or inverters of the internal logic block 21 and the inputs of the level converters 221, 222, . . . 22m of the output buffer 22 are connected in various forms.

The output buffer 22 has the plurality of CMOS-TTL level converters 221, 222, . . . 22m, the respective outputs of which are connected to terminal No. 20, terminal No. 21, . . . terminal No. 29.

The essential features of the level converters 201, 202, . . . 20n of the input buffer 20 are as stated below.

(1) The input threshold voltage V_(ith) of each of the level converters 201, 202, . . . 20n is set between a TTL low level input voltage of 0.8 volt and a TTL high level input voltage of 2.0 volts.

(2) An output transistor, which executes the charge or discharge of the output capacitance C_(s) of each of the level converters 201, 202, . . . 20n in response to an input signal supplied to the input terminal thereof, is formed of a bipolar transistor.

Further, meritorious features in preferable aspects of performance of the level converters 201, 202, . . . 20n of the input buffer 20 are as stated below (noting that the transistors referred to below are in conjunction with FIGS. 14 to 31 discussed in detail hereinafter).

(3) A Schottky barrier diode is connected between the base and collector of the bipolar output transistor Q₁ which executes the discharge of the output capacitance C_(s) in the above item (2).

(4) A second Schottky barrier diode is connected between the base and collector of a driver transistor Q₂ which serves to drive the base of the bipolar output transistor Q₁ with its output in response to the input signal supplied to the input terminal of each of the level converters 201, 202, . . . 20n.

(5) The output transistor which executes the charge of the output capacitance C_(s) of each of the level converters 201, 202, . . . 20n is also formed of a bipolar transistor Q₃.

(6) The base signal or collector signal of the driver transistor Q₂ is transmitted to the base of the charging bipolar output transistor Q₃ through a MOS buffer which has a high input impedance and an amplifying function.

(7) A Schottky barrier diode D₁ for level shift is connected between the input terminal of each of the level converters 201, 202, . . . 20n and the base of the driver transistor Q₂.

(8) A P-N-P emitter follower transistor Q₄ and a P-N junction diode for level shift D₂ are connected between the input terminal of each of the level converters 201, 202, . . . 20n and the base of the driver transistor Q₂.

FIGS. 14 to 31 show diagrams of various circuits of the level converter 201 of the input buffer 20 according to embodiments of the present invention. All these level converters have the essential features of the above items (1) and (2). Further, these level converters have at least one of the meritorious features of the above items (3) to (8).

In the level converter 201 of FIG. 14, the input terminal IN₁ is connected to the cathode of the Schottky barrier diode for level shift D₁, the anode of which is connected to the base of the driver transistor Q₂. The kind of the barrier metal of this diode D₁ and the barrier area thereof are determined so as to set the forward voltage V_(F) thereof at 0.35 volt to 0.41 volt. The forward voltages V_(F) of the Schottky barrier diodes D₁ of the level converters in FIGS. 15 to 31 are similarly set at 0.35 volt to 0.41 volt.

Further, in the arrangement of FIG. 14, each of the driver transistor Q₂ and the discharging output transistor Q₁ has a Schottky barrier diode D connected between the base and collector thereof as indicated by the hook-shaped base electrode symbol thereof. As is well known, the clamped transistor provided with the Schottky barrier diode in this manner has a very short storage time. In the ensuing embodiments, transistors having hook-shaped base electrode symbols are such clamped transistors. The base of the discharging output transistor Q₁ is connected to a ground potential point through a resistor of 5 kiloohms R₁₀ for discharging the base charges thereof.

Besides, in the arrangement of FIG. 14, a resistor of 18 kiloohms R₁₁ and a resistor of 2 kiloohms R₁₂ are connected in series between the supply voltage V_(CC) and the anode of the Schottky barrier diode D₁. The node of both the resistors R₁₁ and R₁₂ is connected to the gate of a P-channel MOS FET M_(p10) which serves as a phase inverter, and the drain of which is connected to the base of the charging output transistor Q₃.

Further, a diode D₃ is connected in order to reliably turn "off" the transistor Q₃ when the level converter 201 produces its low level output. The output of the level converter 201 at the emitter of the charging output transistor Q₃ is connected to the output capacitance C_(s), and is also connected to one input of the CMOS.NAND gate 211 of the internal logic block 21.

The emitter area of each of the bipolar transistors Q₁, Q₂ and Q₃ is set at 100 μm² to 144 μm², and can also be set at a still smaller area. Further, the ratio W/L of each MOS FET is set at a value of 32/3 to 64/3.

It has been confirmed by the inventors that the embodiment of FIG. 14 having the above arrangement exhibits propagation delay times and the output capacitance-dependencies thereof listed below:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.6 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.7 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

It can be appreciated that the aforementioned propagation delay times t_(pHL), t_(pLH) and output capacitance-dependencies K_(HL), K_(LH) are excellent as compared with the characteristics of the input buffer 10 in FIG. 2.

Moreover, the level converter 201 in FIG. 14 can attain desired characteristics for reasons stated below.

(1) The forward voltage V_(F) of the Schottky barrier diode D₁ is set at 0.35 to 0.41 volt, and the base-emitter voltages V_(BE1), V_(BE2) of the transistors Q₁, Q₂ are approximately 0.75 volt. Therefore, the input threshold voltage V_(ith) of the level converter 201 is set as follows: ##EQU1##

(2) The output transistors Q₁, Q₃ for executing the charge or discharge of the output capacitance C_(s) of the level converter 201 are formed of the bipolar transistors of low output resistances. Therefore, the switching operation speeds can be raised or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) The Schottky barrier diode is connected between the base and collector of each of the transistors Q₁, Q₂ which are driven into their saturation regions. Therefore, when both the transistors Q₁, Q₂ operate to switch from "on" into "off", the storage times can be shortened.

(4) When the potential of the node of the resistors R₁₁ and R₁₂ rises to turn "off" the phase inverting MOS FET M_(p10) and the charging output transistor Q₃, current to flow from the node into the gate of the MOS FET M_(p10) becomes very small because the input impedance of the gate of the MOS FET M_(p10) is very high. Accordingly, the embodiment enhances an operating speed for switching the charging output transistor Q₃ from "off" into "on" when compared with a case of forming the phase inverter by the use of a bipolar transistor, not the MOS FET M_(p10).

The level converter 201 of FIG. 15 differs from that of FIG. 14 only in that another P-N junction diode D₄ is added. Such addition of the diode D₄ makes it possible to lower the low level output voltage of the level converter still more.

Regarding the level converter 201 of FIG. 15, the propagation delay times and the output capacitance-dependencies thereof have been confirmed as follows by the inventors:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.89 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           6.37 nsec                                            K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, also the level converter 201 of FIG. 15 can attain desired characteristics for the same reasons as in the case of FIG. 14.

The level converter 201 of FIG. 16 differs from that of FIG. 14 only in the collector connection of the driver transistor Q₂. The propagation delay times and their output capacitance-dependencies of such level converter in FIG. 17 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.81 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.08 nsec                                            K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Also the level converter 201 of FIG. 16 can attain desired characteristics for the same reasons as in the case of FIG. 14.

The level converter 201 of FIG. 17 differs from that of FIG. 15 only in that another N-P-N transistor Q₅ is connected between the drain of the phase inverting MOS FET M_(p10) and the base of the charging output transistor Q₃. The propagation delay times and their output capacitance-dependencies of such level converter in FIG. 17 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           2.01 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           7.30 nsec                                            K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

In the level converter 201 of FIG. 18, the transistors Q₁, Q₂ are clamped transistors with Schottky barrier diodes, and the base of the discharging output transistor Q₁ is connected to the ground potential point through the resistor of 5 kiloohms R₁₀ for discharging base charges. In addition, a resistor of 20 kiloohms R₁₃ for limiting a collector current is connected to the collector of the transistor Q₂.

The resistor of 18 kiloohms R₁₁ and the resistor of 2 kiloohms R₁₂ are connected in series between the supply voltage V_(CC) and the anode of the Schottky barrier diode D₁. The node of both the resistors R₁₁ and R₁₂ is connected to the gate of a P-channel MOS FET M_(p11) serving as a charging output transistor. In addition, the ratio W/L of this FET M_(p11) is 64/3.

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 18 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.9 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           2.9 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  1.3 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 18 can attain desired characteristics for reasons stated below.

(1) Likewise to the case of FIG. 14, the input threshold voltage V_(ith) of the level converter 201 can be set at 1.09 to 1.15 volt.

(2) The output transistor Q₁ for executing the discharge of the output capacitance C_(s) of the level converter 201 is formed of the bipolar transistor of low output resistance. Therefore, the speed of a switching operation at the discharge of the output capacitance can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Likewise to the case of FIG. 14, the storage times of the transistors Q₁, Q₂ can be shortened.

In the level converter 201 of FIG. 19, the transistors Q₁, Q₂ are the clamped transistors with the Schottky barrier diodes, and the base of the discharging output transistor Q₁ is connected to the ground potential point through the resistor of 5 kiloohms R₁₀ for discharging base charges. A load resistor of 8 kiloohms R₁₅ is connected to the collector of the transistor Q₂, and a resistor of 20 kiloohms R₁₄ is incorporated between the supply voltage V_(CC) and the anode of the Schottky barrier diode D₁. The collector signal of the driver transistor Q₂ is applied to the gate of an N-channel MOS FET M_(n12) which serves as a charging output transistor. In addition, the ratio W/L of this FET M_(n12) is set at 64/3.

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 19 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.1 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           8.6 nsec                                             K.sub.HL                  0.3 nsec/pF                                          K.sub.LH                  2.0 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 of FIG. 19 can attain desired characteristics for reasons similar to those in the case of FIG. 18.

In the level converter 201 of FIG. 20, the transistors Q₁, Q₂ are similarly the clamped transistors, and the base of the discharging output transistor Q₁ is connected to the ground potential point through the resistor of 5 kiloohms R₁₀ for discharging base charges. A load resistor of 10 kiloohms R₁₆ is connected to the collector of the transistor Q₂, and the resistor of 20 kiloohms R₁₄ is connected between the supply voltage V_(CC) and the anode of the Schottky barrier diode D₁. The collector signal of the driver transistor Q₂ is applied to the gate of an N-channel MOS FET M_(n13) serving as an amplifier transistor. The ratio W/L of the FET M_(n13) is set at 32/3, and a load resistor of 20 kiloohms R₁₇ is connected to the drain of the FET M_(n13). The drain signal of the FET M_(n13) is applied to the gate of a P-channel MOS FET M_(p13) serving as an amplifier transistor. The ratio W/L of the FET M_(p13) is set at 64/3, and a resistor of 10 kiloohms R₁₈ which serves as a load resistor and also as a resistor for discharging the base charges of the charging bipolar output transistor Q₃ is connected to the drain of the FET M_(p13).

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 20 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           2.2 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           7.5 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 20 can attain desired characteristics for reasons stated below.

(1) Likewise to the case of FIG. 14, the input threshold voltage V_(ith) of the level converter 201 can be set at 1.09 to 1.15 volt.

(2) Likewise to the case of FIG. 14, the speed of a switching operation for the charge or discharge of the output capacitance C_(s) can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Likewise to the case of FIG. 14, the storage times of the transistors Q₁, Q₂ can be shortened.

(4) When the collector potential of the driver transistor Q₂ rises to operate the charging output transistor Q₃ so as to switch from "off" into "on", the amplifier MOS FETs M_(n13) and M_(p13) amplify the change of the collector potential of the transistor Q₂ and transmit the amplified signal to the base of the transistor Q₃. Moreover, since the gate input impedance of the MOS FET M_(n13) is very high, a large base current is inhibited from directly flowing from the collector of the transistor Q₂ into the base of the transistor Q₃. Therefore, the switching speed of the output transistor Q₃ can be enhanced.

In the level converter 201 of FIG. 21, Q₁ and Q₂ indicate the clamped transistors, and D₁ indicates the Schottky barrier diode for level shift. The resistors R₁₀, R₁₄ and R₁₅ are respectively set at 5 kiloohms, 20 kiloohms and 8 kiloohms. The collector signal of the driver transistor Q₂ is applied to both the gates of a P-channel MOS FET M_(p14) and an N-channel MOS FET M_(n14) which constitute a CMOS inverter serving as a voltage amplifier. The drain signal of both the MOS FETs M_(p14), M_(n14) is applied to the gate of the P-channel MOS FET M_(p11) which serves as the charging output transistor. The ratios W/L of the FETs M_(p14), M_(n14) and M_(p11) are respectively set at 24/3, 22/3 and 64/3.

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 21 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           2.02 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           4.27 nsec                                            K.sub.HL                  0.42 nsec/pF                                         K.sub.LH                  1.32 nsec/pF                                         ______________________________________                                    

Further, the level converter 201 in FIG. 21 can attain desired characteristics for the following reasons:

(1) Likewise to the case of FIG. 14, the input threshold voltage V_(ith) of the level converter 201 can be set at 1.09 to 1.15 volt.

(2) The output transistor Q₁ for executing the discharge of the output capacitance C_(s) of the level converter 201 is formed of the bipolar transistor of low output resistance. Therefore, the speed of a switching operation at the discharge of the output capacitance can be enhanced, or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Likewise to the case of FIG. 14, the storage times of the transistors Q₁, Q₂ can be shortened.

In the level converter 201 of FIG. 22, Q₁ indicates the clamped transistor as the discharging output transistor, and the cathode of the level-shifting Schottky barrier diode D₁ is connected to the input terminal IN₁. A P-N junction diode D₅ for level shift is connected between the anode of the diode D₁ and the base of the transistor Q₁, resistors R₁₉ and R₂₀ which are set at equal resistance values of 10 kiloohms are connected in series between the supply voltage V_(CC) and both the anodes of the diodes D₁ and D₅, and a Schottky barrier diode D₆ for discharging base charges is connected between the input terminal IN₁ and the base of the transistor Q₁.

The node of the resistors R₁₉ and R₂₀ is connected to the gate of the P-channel MOS FET M_(p11) serving as the charging output transistor, and the ratio W/L of the FET M_(p11) is set at 64/3.

The propagation delay times and their output capacitance-dependencies of such level converter in FIG. 22 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           2.44 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.41 nsec                                            K.sub.HL                  0.1 nsec/pF                                          K.sub.LH                  5.3 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 22 can attain desired characteristics for the following reasons:

(1) The forward voltage V_(F1) of the Schottky barrier diode D₁ is set at 0.35 to 0.41 volt, the forward voltage V_(F5) of the P-N junction diode D₅ is set at 0.75 volt, and the base-emitter voltage V_(BE1) of the transistor Q₁ is 0.75 volt. Therefore, the input threshold voltage V_(ith) of the level converter 201 for turning "on" the transistor Q₁ is set as below: ##EQU2##

(2) The output transistor Q₁ for executing the discharge of the output capacitance C_(s) is formed of the bipolar transistor of low output resistance. Therefore, the switching times or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Since the transistor Q₁ is the clamped transistor, its storage time can be shortened.

In the level converter 201 of FIG. 23, Q₁ and Q₂ indicate the clamped transistors, and D₁ indicates the Schottky barrier diode for level shift. The resistors R₁₀, R₁₄ and R₁₅ are respectively set at 5 kiloohms, 20 kiloohms and 8 kiloohms. The collector signal of the driver transistor Q₂ is applied to both the gates of the P-channel MOS FET M_(p14) and N-channel MOS FET M_(n14) which constitute the CMOS inverter serving as the voltage amplifier, and the drain output of both the MOS FETs is applied to the gate of a switching P-channel MOS FET M_(p15). The ratios W/L of the FETs M_(p14), M_(n14) and M_(p15) are respectively set at 24/3, 32/3 and 64/3.

The drain output of the MOS FET M_(p15) is applied to the base of the bipolar transistor Q₃ which serves as the charging output transistor.

The propagation delay times and their output capacitance-dependencies of such level converter in FIG. 23 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           5.07 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.09 nsec                                            K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 23 can attain desired characteristics for the following reasons:

(1) Likewise to the case of FIG. 14, the input threshold voltage V_(ith) of the level converter 201 can be set at 1.09 to 1.15 volt.

(2) Likewise to the case of FIG. 14, the switching times for the charge and discharge of the output capacitance C_(s) or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Likewise to the case of FIG. 14, the storage times of the transistors Q₁, Q₂ can be shortened.

(4) When the collector potential of the driver transistor Q₂ rises to operate the charging output transistor Q₃ so as to switch from "off" into "on", the CMOS inverter M_(p14), M_(n14) amplifies the change of the collector potential of the transistor Q₂ and transmits the amplified signal to the base of the transistor Q₃. Moreover, since the gate input impedances of the MOSFETs M_(p14), M_(n14) are very high, a large base current is inhibited from directly flowing from the collector of the transistor Q₂ into the base of the transistor Q₃. Therefore, the switching speed of the output transistor Q₃ can be enhanced.

The level converter 201 of FIG. 24 differs from that of FIG. 23 only in that the resistor of 10 kiloohms R₁₈ for discharging the base charges of the charging output transistor Q₃ is connected between the base and emitter of the transistor Q₃. Regarding such level converter 201 in FIG. 24, the propagation delay times and their output capacitance-dependencies have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           6.2 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           4.9 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 24 can attain desired characteristics for reasons similar to those in the case of FIG. 23.

The level converter 201 of FIG. 25 differs from that of FIG. 24 only in that the resistor R₁₀ of the base charge discharging circuit of the discharging output transistor Q₁ is replaced with an active pull-down circuit which is constructed of a resistor of 1.5 kiloohm R₁₉, a resistor of 3 kiloohms R₂₀ and a clamped transistor Q₆, and that a Schottky barrier diode D₇ for discharging the base charges of the charging output transistor Q₃ is connected between the base of the transistor Q₃ and the collector of the transistor Q₂. Regarding such arrangement of FIG. 25, the propagation delay times and their output capacitance-dependencies have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           6.6 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.3 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 25 can attain desired characteristics for reasons similar to those in the case of FIG. 23.

The level converter 201 of FIG. 26 differs from that of FIG. 24 only in that the discharging resistor R₁₀ is replaced with the same active pull-down circuit as the active pull-down circuit R₁₉, R₂₀, Q₆ in FIG. 25. Regarding such arrangement of FIG. 26, the propagation delay times and their output capacitance-dependencies have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           8.62 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           4.7 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.4 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 26 can attain desired characteristics for reasons similar to those in the case of FIG. 23.

In the level converter 201 of FIG. 27, the bipolar transistors Q₁, Q₂ and Q₃ are respectively the discharging output transistor, driver transistor and charging output transistor. D₁ and D₈ indicate the Schottky barrier diode for level shift and a P-N junction diode, respectively. R₁₄, R₁₆, R₂₁ and R₂₂ indicate resistors of 20 kiloohms, 8 kiloohms, 10 kiloohms and 10 kiloohms, respectively. M_(p16) and M_(n16) indicate a P-channel MOS FET and an N-channel MOS FET respectively, and both the ratios W/L of the two FETs M_(p16) and M_(n16) are set at equal values of 32/3.

In particular, the embodiment is characterized in that the transistors M_(p16), M_(n16), Q₁ and Q₃ constitute an amplifier of the quasi-CMOS inverter type of low output resistance.

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 27 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           5.48 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.23 nsec                                            K.sub.HL                  0.37 nsec/pF                                         K.sub.LH                  0.38 nsec/pF                                         ______________________________________                                    

Further, the level converter 201 in FIG. 27 can attain desired characteristics for reasons stated below.

(1) The forward voltage V_(F1) of the Schottky barrier diode D₁ is set at 0.35 to 0.41 volt, the base-emitter voltage V_(BE2) of the transistor Q₂ at 0.75 volt, and the forward voltage V_(F8) of the P-N junction diode D₈ at 0.75 volt. Therefore, the input threshold voltage V_(ith) of the level converter 201 concerning the on-off operation of the transistor Q₂ is set as follows: ##EQU3##

(2) The output transistors Q₁, Q₃ for executing the charge or discharge of the output capacitance C_(s) are formed of the bipolar transistors of low output resistances. Therefore, the switching operation speeds can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Since the transistors Q₁, Q₂ are the clamped transistors, their storage times can be shortened.

(4) Since the change of the collector potential of the driver transistor Q₂ is amplified and then transmitted to the output end by the quasi-CMOS inverter M_(p16), M_(n16), Q₃, Q₁, the changing speed of an output waveform can be enhanced.

The level converter 201 of FIG. 28 differs from that of FIG. 27 only in that the collector load of the transistor Q₂ is not formed of the resistor R₁₆, but is formed of P-N junction diodes D₉, D₁₀ and a resistor of 5 kiloohms R₂₃. The propagation delay times and their output capacitance-dependencies of such level converter in FIG. 28 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           6.66 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           4.16 nsec                                            K.sub.HL                  0.42 nsec/pF                                         K.sub.LH                  0.37 nsec/pF                                         ______________________________________                                    

Further, the level converter 201 in FIG. 28 can attain desired characteristics for reasons similar to those in the case of FIG. 27.

The level converter 201 of FIG. 29 differs from that of FIG. 23 only in the point of connecting the P-N junction diode D₃ for reliably turning "off" the transistor Q₃ and in the point of connecting the Schottky barrier diode D₇ for discharging the base charges of the transistor Q₃. Regarding such level converter 201 in FIG. 29, the propagation delay times and their output capacitance-dependencies have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.72 nsec                                            t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.44 nsec                                            K.sub.HL                  0.32 nsec/pF                                         K.sub.LH                  0.29 nsec/pF                                         ______________________________________                                    

Further, the level converter 201 in FIG. 29 can attain desired characteristics for reasons similar to those in the case of FIG. 23.

The level converter 201 of FIG. 30 differs from that of FIG. 29 only in that the resistor R₁₄ in FIG. 29 is substituted by a resistor of 25 kiloohms R₂₄ and a resistor of 5 kiloohms R₂₅, and that the resistor R₁₅ is substituted by a P-channel MOS FET M_(p17) whose ratio W/L is set at 24/3. Since the FET M_(p17) operates as the active load element of the transistor Q₂, the voltage gain of the amplifier Q₂, M_(p17) becomes a very large value. Regarding such arrangement of FIG. 30, the propagation delay times and their output capacitance-dependencies have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           2.2 nsec                                             t.sub.pLH (for C.sub.s = 0 pF)                                                                           5.2 nsec                                             K.sub.HL                  0.4 nsec/pF                                          K.sub.LH                  0.3 nsec/pF                                          ______________________________________                                    

Further, the level converter 201 in FIG. 30 can attain desired characteristics for reasons similar to those in the case of FIG. 23.

In the level converter 201 of FIG. 31, the transistors Q₁ and Q₂ are the clamped transistors, the transistor Q₃ is the charging output transistor, a transistor Q₄ is a P-N-P emitter follower transistor, the diode D₁ is the Schottky barrier diode for level shift, the diode D₂ is the P-N junction diode for level shift, the diode D₃ is the P-N junction diode for reliably turning "off" the transistor Q₃, and the diode D₈ is the Schottky barrier diode for clamping minus noise at the input terminal. Resistors R₁₀, R₁₅ and R₂₆ are respectively set at 5 kiloohms, 8 kiloohms and 20 kiloohms. The collector signal of the driver transistor Q₂ is applied to both the gates of the P-channel MOS FET M_(p14) and N-channel MOS FET M_(n14) which constitute the CMOS inverter serving as the voltage amplifier, and the drain output of which is applied to the gate of the switching P-channel MOS FET M_(p15). The ratios W/L of the FETs M_(p14), M_(n14) and M_(p15) are respectively set at 24/3, 32/3 and 64/3. The drain output of the MOS FET M_(p15) is applied to the base of the bipolar transistor Q₃ serving as the charging output transistor.

The propagation delay times and their output capacitance-dependencies of such level converter 201 in FIG. 31 have been confirmed as follows:

    ______________________________________                                         t.sub.pHL (for C.sub.s = 0 pF)                                                                           1.94 - 3.84 nsec                                     t.sub.pLH (for C.sub.s = 0 pF)                                                                           4.64 - 5.44 nsec                                     K.sub.HL                  0.38 nsec/pF                                         K.sub.LH                  0.30 nsec/pF                                         ______________________________________                                    

Further, the level converter 201 in FIG. 31 can attain desired characteristics for reasons stated below.

(1) The forward voltage V_(F1) of the Schottky barrier diode D₁ is 0.35 to 0.41 volt, the forward voltage V_(F2) of the P-N junction diode D₂ is approximately 0.75 volt, and the base-emitter voltages V_(BE1), V_(BE2) and V_(BE4) of the respective transistors Q₁, Q₂ and Q₄ are approximately 0.75 volt. Therefore, the input threshold voltage V_(ith) at which the transistors Q₁, Q₂ are turned "on" becomes as follows: ##EQU4##

(2) The output transistors Q₁, Q₃ for executing the discharge or charge of the output capacitance C_(s) are formed of the bipolar transistors of low output resistances. Therefore, the speeds of switching operations can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Since the transistors Q₁, Q₂ are the clamped transistors, their storage times can be shortened.

(4) When the collector potential of the driver transistor Q₂ rises to operate the charging bipolar output transistor Q₃ to switch from "off" into "on", the CMOS inverter M_(p14), M_(n14) amplifies the change of the collector potential of the transistor Q₂ and transmits the amplified signal to the base of the transistor Q₃. Moreover, the gate input impedances of the MOS FETs M_(p14), M_(n14) are very high and inhibit the direct flow of a large base current from the collector of the transistor Q₂ into the base of the transistor Q₃, and a base current is supplied to the base of the transistor Q₃ through the low ON-resistance of the FET M_(p15). Therefore, the switching speed of the output transistor Q₃ can be enhanced. FIG. 3 shows with dot-and-dash lines the output capacitance-dependencies of the propagation delay times of the level converters illustrated in FIGS. 14, 19, 22 and 31. It is understood that the output capacitance-dependency of either of the first and second propagation delay times is improved.

There will now be explained the plurality of CMOS - TTL level converters 221, 222, . . . 22m of the output buffer 22 in FIG. 6. The essential feature of these level converters 221, 222, . . . 22m are as stated below.

(1) The input threshold voltage V_(ith) of each of the level converters 221, 222, . . . 22m is set between a CMOS low level output voltage of 0.6 volt and high level output voltage of 4.4 volts.

(2) An output transistor, which executes the discharge of the output load capacitance C_(x) of each of the level converters 221, 222, . . . 22m in response to an input signal supplied to the input terminal thereof, is formed of a bipolar transistor.

Further, meritorious features in preferable aspects of performance of the level converters 221, 222, . . . 22m of the output buffer 22 are as stated below (noting that the transistors referred to pertain to FIGS. 32 to 34 and 36 which will be described in detail hereinafter).

(3) A high input impedance circuit is connected between the output of the internal logic block 21 and the base of a driver transistor Q₁₁ for driving the base of a discharging output transistor Q₁₀.

(4) The high input impedance circuit in the above item (3) has the function of logically processing a plurality of output signals from the internal logic block 21.

(5) The discharging output transistor Q₁₀ and the driver transistor Q₁₁ are formed of clamped transistors provided with Schottky barrier diodes.

(6) An output transistor Q₁₂ for charging the output load capacitance C_(x) is formed of a bipolar transistor.

(7) The level converter has the function of simultaneously turning "off" the discharging output transistor Q₁₀ and the charging output transistor Q₁₂ in response to a control signal, thereby to control the corresponding output terminal, e.g., OUT₁ into a floating state.

(8) The level converters 221, 222, . . . 22m are of the open collector output form.

FIGS. 32 to 34 and FIG. 36 show various examples of circuits of the level converter 221 of the output buffer 22 according to embodiments of the present invention. All these level converters have the essential features of the above items (1) and (2). Further, these level converters have at least one of the meritorious features of the above items (3) to (8).

In the level converter 221 of FIG. 32, Q₁₀ designates the output transistor for discharging the output load capacitance C_(x), Q₁₁ the driver transistor for driving the transistor Q₁₀, Q₁₂ the output transistor for charging the output load capacitance C_(x), and Q₁₃ a current amplifying transistor for transmitting the collector signal change of the transistor Q₁₁ to the base of the transistor Q₁₂. Components R₃₀, R₃₁ and Q₁₄ constitute an active pull-down circuit for discharging the base charges of the transistor Q₁₀. Q₁₅ indicates a multi-emitter transistor, R₃₂ the collector resistor of the transistor Q₁₁, R₃₃ a resistor for discharging the base charges of the transistor Q₁₂, D₁₀ a Schottky barrier diode for discharging the base charges of the transistor Q₁₂, R₃₄ a resistor for limiting the collector currents of the transistors Q₁₂ and Q₁₃, and R₃₅ the base resistor of the transistor Q₁₅.

Further, the output of the CMOS·NAND gate 211 of the internal logic block 21, this gate being composed of P-channel MOS FETs M₁, M₂ and N-channel MOS FETs M₃, M₄, is applied to the first emitter of the multi-emitter transistor Q₁₅ ; the output of the CMOS·NAND gate 212 is applied to the second emitter of the transistor Q₁₅ ; and the output of the CMOS·NAND gate 213 is applied to the third emitter of the transistor Q₁₅. The level converter 221 accordingly has, not only a level converting function, but also a logical processing function as a 3-input NAND gate.

Moreover, the level converter 221 in FIG. 32 can attain desired characteristics for reasons stated below.

(1) The base-emitter voltage V_(BE15) of the transistor Q₁₅ is approximately 0.75 volt, the base-collector voltage V_(BC15) of the transistor Q₁₅ is approximately 0.55 volt, and the base-emitter voltages V_(BE10) and V_(BE11) of the respective transistors Q₁₀ and Q₁₁ are approximately 0.75 volt. Therefore, the input threshold voltage V_(ith) of the level converter 221 is set as follows: ##EQU5##

(2) The output transistors Q₁₀, Q₁₂, which execute the discharge or charge of the output load capacitance C_(x) of the level converter 221, are formed of bipolar transistors of low output resistances. Therefore, the speeds of switching operations can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) Since the transistors Q₁₀, Q₁₁, Q₁₃, Q₁₄ and Q₁₅ are the clamped transistors, their storage times can be shortened.

(4) Since the multi-emitter transistor Q₁₅ has the logical processing function, the design versatility of the logic semiconductor integrated circuit IC of the master slice type or the gate array type is enhanced.

In such level converter 221 of FIG. 32, however, when the output of the CMOS·NAND gate 211 is at its low level, a relatively large current of 0.4 milliampere continues to flow from the supply voltage V_(CC) to the output end of the CMOS·NAND gate 211 through the resistor R₃₅ as well as the base-emitter junction of the transistor Q₁₅. Therefore, the ratios W/L of the N-channel MOS FETs M₃, M₄ of the CMOS·NAND gate 211 must be set at large values of 100/3 so as to lower ON-resistances R_(ON). This incurs lowering in the density of integration of the integrated circuit IC. Moreover, the inventors' study has revealed the problem that, since the gate capacitances of both the MOS FETs M₃ and M₄ increase, the switching speed of the CMOS·NAND gate 211 lowers.

FIG. 33 shows a circuit diagram of the level converter 221 which has been developed in order to solve the problems described above, and in which the multi-emitter transistor Q₁₅ in FIG. 32 is substituted by the high input impedance circuit to be explained below.

Referring to FIG. 33, the high input impedance circuit shown there is constructed of P-N-P input transistors Q₁₇, Q₁₈, an N-P-N emitter follower transistor Q₁₆, Schottky barrier diodes D₁₁, D₁₂ and resistors R₃₆, R₃₇, R₃₈.

Further, the level converter 221 includes a control circuit which is constructed of a P-N-P transistor Q₂₀, an N-P-N transistor Q₂₁, a P-N junction diode D₁₄ and a resistor R₃₈, and which serves to control the output terminal OUT₁ into the floating state.

The base of the P-N-P transistor Q₂₀ of this control circuit is driven by the enable signal EN of the CMOS inverter 21l in the internal logic block 21, this inverter being composed of a P-channel MOS FET M₅ and an N-channel MOS FET M₆. The input of such CMOS inverter 21l is supplied with the inverted enable signal EN.

Further, since this control circuit has been added to the level converter 221, a P-N-P input transistor Q₁₉ and a Schottky barrier diode D₁₃ are also added to the aforementioned high input impedance circuit.

Accordingly, when the enable signal EN becomes its low level, the transistors Q₁₀, Q₁₁, Q₁₂ and Q₁₃ of the level converter 221 turn "off" at the same time, so that the output terminal OUT₁ falls into the floating state.

On the other hand, when the enable signal EN becomes its high level, the level converter 221 similarly has a logical processing function as a 2-input NAND gate, so that the design versatility of the integrated circuit IC is enhanced.

Further, the forward voltages V_(F11), V_(F12), V_(F13) of the respective Schottky barrier diodes D₁₁, D₁₂, D₁₃ are 0.35 to 0.41 volt, the base-emitter voltages V_(BE17), V_(BE18), V_(BE19) of the respective P-N-P input transistors Q₁₇, Q₁₈, Q₁₉ are approximately 0.75 volt, and the base-emitter voltages V_(BE10), V_(BE11), V_(BE16) of the respective N-P-N transistors Q₁₀, Q₁₁, Q₁₆ are approximately 0.75 volt. Therefore, the input threshold voltage V_(ith) at which the transistors Q₁₀ and Q₁₁ turn "on" in relation to, e.g., the output voltage of the CMOS·NAND gate 211 applied to the base of the P-N-P transistor Q₁₇ becomes as follows: ##EQU6##

Moreover, the output transistors Q₁₀, Q₁₂ for executing the discharge or charge of the output load capacitance C_(x) are formed of the bipolar transistors of low output resistances. Therefore, the switching speeds can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened. In addition, since the transistors Q₁₀, Q₁₁, Q₁₃, Q₁₄ and Q₁₆ are the clamped transistors, their delay times can be shortened.

The inventors' study, however, has revealed that, even with the level converter 221 of FIG. 33, an unnegligible current still flows from the base of the P-N-P input transistor Q₁₇ to the output end of the CMOS·NAND gate 211 when the output of this gate 211 is at the low level, so the foregoing problems cannot be perfectly solved.

FIG. 34 shows the level converter 221 which has been finally developed in order to solve such problems substantially perfectly. The multi-emitter transistor Q₁₅ in FIG. 32 is replaced with the high input impedance circuit which is constructed of MOS FETs as explained below.

Referring to FIG. 34, the high input impedance circuit shown there is constructed of N-channel MOS FETs M₁₁, M₁₂, M₁₃ and a P-N junction diode D₁₄. The drain-source paths of the FETs M₁₁, M₁₂, M₁₃ are connected in parallel, and the gates thereof are respectively connected to the CMOS·NAND gates 211, 212, 213 of the internal logic block 21. In addition, the P-N junction diode D₁₄ is connected in series with the drain-source paths.

Resistors R₃₀, R₃₁, R₃₂, R₃₃, R₃₄ and R₃₅ are respectively set at 2 kiloohms, 4 kiloohms, 10 kiloohms, 4 kiloohms, 50-75 ohms and 16 kiloohms. The emitter areas of the transistors Q₁₀, Q₁₁, Q₁₂, Q₁₃ and Q₁₄ are respectively set at 672 μm², 132 μm², 363 μm², 187 μm² and 242 μm².

Further, in such level converter 221, in order to enhance the logic processing function still more, a second driver transistor Q₂₀ which has an emitter area equal to that of the driver transistor Q₁₁ is connected in parallel with the transistor Q₁₁, and a second high input impedance circuit is disposed which is constructed of N-channel MOS FETs M₁₄, M₁₅, M₁₆, a P-N junction diode D₁₅ and a resistor R₃₉ likewise to the foregoing high input impedance circuit. This level converter 221 has a logic processing function as a 6-input complex gate circuit.

Further, a control circuit is similarly added to this level converter 221, the control circuit serving to control the output terminal OUT₁ into the floating state when the level converter is supplied with the enable signal EN of low level from the internal logic block 21. This control circuit is constructed of an N-channel MOS FET M₁₇, transistors Q₂₁, Q₂₂, Q₂₃, resistors R₄₀, R₄₁, R₄₂, R₄₃, and Schottky barrier diodes D₁₆, D₁₇, D₁₈, D₁₉.

Further, in the level converter 221 of FIG. 34, in order to set input threshold voltages at the respective gates of the six MOS FETs M₁₁, . . . M₁₆ at the middle value of 2.5 volts between the CMOS low level output voltage of 0.6 volt and the CMOS high level output voltage of 4.4 volts, the ratios W/L of the FETs M₁₁, . . . M₁₆ are set as stated below. At this time, the threshold voltages V_(TH) of the FETs M₁₁, . . . M₁₆ are set at approximately 0.75 volt, the forward voltage V_(F14) of the P-N junction diode D₁₄ is set at 0.75 volt, and the channel conductances β₀ of the FETs M₁₁, . . . M₁₆ are set at 60×10⁻⁶ [1/ohm].

A case where only the MOS FET M₁₁ is "on" will be considered, and the gate voltage V_(X), gate-source voltage V_(GS), drain current I_(D), drain voltage V_(Y) etc. thereof will be calculated. At this time, the FET M₁ is supposed to be biased in its saturation region. ##EQU7## From Equations (1) and (2), ##EQU8##

Considered as the input threshold voltage is the voltage V_(X) which corresponds to the fact that the voltage V_(Y) lowers due to a rise in the voltage V_(X), resulting in the turn-off of the transistors Q₁₀, Q₁₁.

The drain voltage V_(Y) at which the transistors Q₁₀, Q₁₁ turn "off" is evaluated as follows:

    V.sub.Y =V.sub.BE11 +V.sub.BE10                            (5)

From Equations (3) and (5), ##EQU9##

From Equations (4) and (6), ##EQU10##

Substituting into Equation (7) the conditions of V_(CC) being 5 volts, V_(BE11) and V_(BE10) being 0.75 volt, R₃₅ being 16 kiloohms, β₀ being 60×10⁻⁶ [1/ohm], V_(X) being 2.5 volts, V_(F14) being 0.75 volt and V_(TH) being 0.75 volt, ##EQU11##

Thus, the input threshold voltage of the level converter 221 can be set at 2.5 volts by setting the ratios W/L of the FETs M₁₁, . . . M₁₆ at 22/3.

The embodiment of FIG. 34 having the above arrangement has been confirmed by the inventors to exhibit the propagation delay times and the output capacitance-dependencies thereof as listed below.

    ______________________________________                                         t.sub.pHL (for C.sub.x = 0 pF)                                                                           8.8 nsec                                             t.sub.pLH (for C.sub.x = 0 pF)                                                                           7.8 nsec                                             K.sub.HL                  0.11 nsec/pF                                         K.sub.LH                  0.01 nsec/pF                                         ______________________________________                                    

FIG. 5 shows with dot-and-dash lines the output load capacitance-dependencies of the propagation delay times of the level converter 221 of the embodiment illustrated in FIG. 34. It is understood that the respective output capacitance-dependencies K_(HL), K_(LH) of the first and second propagation delay times t_(pHL), t_(pLH) are improved.

The level converter 221 in FIG. 34 can attain desired characteristics for reasons stated below.

(1) As described above, the ratios W/L of the MOS FETs M₁₁, . . . M₁₆ are set in correspondence with the supply voltage V_(CC), the resistance R₃₅, the channel conductances β₀ and threshold voltages V_(TH) of the MOS FETs M₁₁, . . . M₁₆, and the forward voltage V_(F14) of the diode D₁₄ concerning the base-emitter voltages V_(BE10), V_(BE11) of the transistors Q₁₀, Q₁₁, whereby the input threshold voltage of the level converter 221 can be set at 2.5 volts which is between 0.6 volt and 4.4 volts.

(2) The output transistors Q₁₀, Q₁₁ which execute the discharge and charge of the output load capacitance C_(X) are formed of the bipolar transistors of low output resistances. Therefore, the switching operation speeds can be enhanced or the propagation delay times can be shortened, and the output capacitance-dependencies of the propagation delay times can be lessened.

(3) The high input impedance circuit including the MOS FET M₁₁ is connected between the base of the driver transistor Q₁₁ and the output of the internal logic block 21. Therefore, current to flow from the gate of the MOS FET M₁₁ to the output of the CMOS·NAND gate 211 of the internal logic block 21 can be reduced to a negligible level, and a conspicuous increase in the ratio W/L of the N-channel MOS FETs of the CMOS·NAND gate 211 can be prevented.

(4) Since the MOS FETs M₁₁, M₁₂, M₁₃ of the high input impedance circuit execute 3-input OR logic, the logical processing function of the level converter 221 is enhanced.

(5) Since also the two driver transistors Q₁₁, Q₂₀ execute AND logic, the logical processing function of the level converter 221 is further enhanced.

(6) Since the transistors Q₁₀, Q₁₁, Q₁₃, Q₁₄, Q₂₀ are clamped transistors, their storage times can be shortened.

(7) By bringing the enable signal EN into the low level, the output transistors Q₁₀, Q₁₂ of the level converter 221 are simultaneously turned "off", so that the output terminal OUT₁ falls into the floating state. Thus, in a parallel operation wherein this output terminal OUT₁ and the output terminal of another logic circuit, not shown, are connected, the signal level of the output terminal OUT₁ can be made independent of the output of the internal logic block 21.

FIG. 36 shows a circuit example of the level converter 221 according to another embodiment of the present invention. The output terminal OUT₁ of this level converter is connected in common with the output terminal of another TTL level logic semiconductor integrated circuit IC' of the open collector output type, and the common connection point is connected to the supply voltage V_(CC) of 5 volts through a load resistor of 2 kiloohms R₁₀₀.

Although not especially restricted, the open collector output type TTL level circuit IC' is constructed of Schottky barrier diodes D₁, D₂, D₃, a multi-emitter transistor Q₄₀, clamped transistors Q₄₁ to Q₄₄, resistors R₄₀ to R₄₄, and a P-N junction diode D₄. As an open collector output, the collector of the output transistor Q₄₃ is connected to terminal No. 43 serving as an output terminal. Inside the circuit IC', however, no circuit element is connected between the supply voltage V_(CC) and the collector of the output transistor Q₄₃.

The level converter 221 of FIG. 36 is formed quite similarly to the level converter 221 of FIG. 34 except that, inside the circuit IC, no circuit element is connected between the supply voltage V_(CC) and the collector of the output transistor Q₁₀.

Thus, the output terminals of the circuit IC and those of the circuit IC' are connected in the form of the so-called wired OR circuit. In addition, the output transistor Q₁₀ of the level converter 221 is forcibly turned "off" by bringing the enable signal EN into the low level, whereby the level of the output terminal OUT₁ can be made independent of the output of the internal logic block 21.

FIG. 37 shows the layout of the various circuit blocks in the front surface of a semiconductor chip of the logic semiconductor integrated circuit IC embodying the present invention.

In the central part (an area enclosed with a broken line l_(o)) of the semiconductor chip 300, the internal logic block 21 formed of the CMOS circuit (pure CMOS circuit or quasi-CMOS circuit) is arranged. In the upper edge part (an area enclosed with a broken line l₁) of the semiconductor chip 300, the plurality of input level converters as shown in FIG. 31 (indicated by triangles whose inner parts are hatched) and the plurality of output level converters as shown in FIG. 34 (indicated by triangles whose inner parts are white) are arranged alternately. Likewise, in each of the right edge part (an area enclosed with a broken line l₂), the lower edge part (an area enclosed with a broken line l₃) and the left edge part (an area enclosed with a broken line l₄) of the semiconductor chip 300, the plurality of input level converters as shown in FIG. 31 and the plurality of output level converters as shown in FIG. 34 are arranged alternately.

Above the upper edge part l₁, bonding pads for inputs (indicated by squares of thick solid lines) corresponding in number to the input level converters and bonding pads for outputs (indicated by squares of thin solid lines) corresponding in number to the output level converters are arranged. The input parts of the input level converters confront the corresponding input bonding pads, while the output parts thereof confront the internal logic block 21, and the input parts of the output level converters confront the internal logic block 21, while the output parts thereof confront the corresponding output bonding pads.

A plurality of input bonding pads and a plurality of output bonding pads on the right of the right edge part l₂, a plurality of input bonding pads and a plurality of output bonding pads below the lower edge part l₃, and a plurality of input bonding pads and a plurality of output bonding pads on the left of the left edge part l₄ are arranged similarly to the case of the upper edge part l₁.

The orientations of the input and output parts of the input level converters and those of the input and output parts of the output level converters in the right edge part l₂, lower edge part l₃ and left edge part l₄ are respectively the same as in the case of the upper edge part l₁.

A power source bonding pad 30 for feeding the supply voltage V_(CC) is arranged in at least one of the four corners of the semiconductor chip 300, and a grounding bonding pad 31 for connection to a ground potential point is arranged in at least one of the four corners.

The rear surface of such semiconductor chip of the layout shown in FIG. 37 is connected to the front surface of the tab lead L_(T) of a metal lead frame L_(F) in FIG. 38 in physical and electrical close contact.

Referring to FIG. 38, this lead frame L_(F) has lead portions L₁ -L₁₆, a frame portion L₀ and hatched dam portions L_(D) which correspond to the right upper part of the semiconductor chip 300. In actuality, however, parts corresponding to the right lower part, left lower part and left upper part of the semiconductor chip are similar to the above. Therefore, the lead frame L_(F) is a worked metal sheet of a structure wherein the frame portion L₀, lead portions L₁ -L₆₄ and tab lead L_(T) are interconnected by the hatched dam portions.

After the rear surface of the semiconductor chip 300 has been connected to the front surface of the tab lead L_(T), bonding wires (for example, gold wires or aluminum wires) to be described below are wired.

Using wire bonding equipment which is commercially available, the power source bonding pad 30 and the lead portion L₃₄ are electrically connected by a wire l₅. Further, the input pad and the lead portion L₉ are electrically connected by a wire l₆, the output pad and the lead portion L₈ by a wire l₇, the input pad and the lead portion L₇ by a wire l₈, the output pad and the lead portion L₆ by a wire l₉, the input pad and the lead portion L₅ by a wire l₁₀, and the grounding bonding pad 31 and the tab lead L_(T) by a wire l₁₁, in succession.

The lead frame L_(T) and the semiconductor chip 300 after the completion of the above wiring are put in a metal mold for resin molding, whereupon a liquid resin is poured inside the dam portions L_(D) of the lead frame L_(F). Such dam portions L_(D) hinder the resin from flowing out of them. After the resin has solidified, the lead frame L_(F), semiconductor chip 300 and resin which form a unitary structure are taken out from the metal mold. Then the dam portions L_(D) are removed by a press machine or the like, whereby the respective lead portions L₁ -L₆₄ can be electrically isolated.

If necessary, the leads L₁ -L₆₄ protruding outside the solidified resin are bent downwards. Then, the logic semiconductor integrated circuit IC molded with the resin 301 is finished up as shown in FIG 39, which shows the completed device. As seen from the figure, such circuit IC is not provided with any special radiation fin for positively radiating heat produced from the semiconductor chip 300, out of the molded structure. If such radiation fin is mounted, the cost of the circuit IC will increase undesirably.

As methods of sealing the semiconductor chip, a ceramic molding method and a method employing a metal case can be used, if desired, instead of the resin molding method stated above. From the viewpoint of the cost of the circuit IC, however, the resin molding method is the most advantageous.

In the logic semiconductor integrated circuit IC according to the embodiment drawn in FIGS. 37 to 39, the total number of the input level converters 201, 202, . . . , 20n constituting the input buffer 20 is 18-50, the total number of the CMOS gates 211, 212, . . . , 21l constituting the internal logic block 21 is 200-1530, and the total number of the output level converters 221, 222, . . . , 22m constituting the output buffer 22 is 18-50, so that the semiconductor chip 300 forms a large-scale semiconductor integrated circuit device. Nevertheless, the circuit IC has been successfully put into the radiation fin-less structure for reasons stated below.

Since the power consumption of each of the CMOS gates 211, 212, . . . , 21l constituting the internal logic block 21 is as slight as 0.039 milliwatt, the power consumption of the whole internal logic block 21 having the 200-1530 gates is as low as 7.8-59.67 milliwatts, which is very low for this number of gates. Since the input level converters 201, 202, . . . , 20n constituting the input buffer 20 according to the embodiment of FIG. 31 include a large number of bipolar transistors, the power consumption per converter is as high as 2.6 milliwatts, and the power consumption of the whole input buffer 20 having the 18-50 converters is as high as 46.8-130 milliwatts. Since also the output level converters 221, 222, . . . , 22m constituting the output buffer 22 according to the embodiment of FIG. 34 include a large number of bipolar transistors, the power consumption per converter is as high as 3.8 milliwatts, and the power consumption of the whole output buffer 22 having the 18-50 converters is as high as 68.4-190 milliwatts.

On the basis of the above data, in the circuit IC which is constructed of the input buffer 20 having the 18 converters, the internal logic block 21 having the 200 gates and the output buffer 22 having the 18 converters, heat of 6.4% with respect to the entire amount of heat is generated in the central part l₀ of the front surface of the semiconductor chip shown in FIG. 37, whereas heat of 93.6% is generated in the edge parts l₁, l₂, l₃ and l₄ in total.

Besides, in the circuit IC which is constructed of the input buffer 20 having the 50 converters, the internal logic block 21 having the 1530 gates and the output buffer 22 having the 50 converters, heat of 15.8% with respect to the entire amount of heat is generated in the central part l₀ of the front surface of the semiconductor chip shown in FIG. 37, whereas heat of 84.2% is generated in the edge parts l₁, l₂, l₃ and l₄ in total.

As illustrated in FIG. 37, the internal logic block 21 which generates the slight heat is arranged in the central part l₀ of the chip, and the input buffer 20 and the output buffer 22 which generate the large quantities of heat are arranged in the edge parts l₁, l₂, l₃ and l₄ of the chip. As seen from FIG. 38, therefore, the large quantities of heat in the edge parts l₁, l₂, l₃ and l₄ are taken out of the circuit IC (particularly, taken out to the ground line of a printed circuit board when the circuit IC is installed on the printed circuit board) through the tab lead L_(T) and the lead portion L₁ as a grounding lead. Moreover, they can be taken out of the circuit IC (particularly, taken out to the signal lines and power source line of the printed circuit board when the circuit IC is installed on the printed circuit board) through the large number of bonding wires and the lead portions L₂, . . . , L₆₄.

It has been confirmed by the inventors' computation that, in a case where conversely to the above embodiment, the input buffer 20 and the output buffer 22 which generate the large quantities of heat are arranged in the central part l₀ of the chip and the internal logic block 21 is arranged around the central part l₀, the large quantities of heat in the central part l₀ cannot be readily taken out of the circuit IC.

For the reasons described above, it has been possible to put the circuit IC of the above embodiment into the radiation fin-less structure. In addition, since such circuit IC has been put into the resin-molded structure, it has become possible to sharply reduce the cost of the circuit IC.

FIG. 40 shows a block diagram of an electronic system which is constructed by installing on a printed circuit board the logic semiconductor integrated circuit IC according to the embodiment illustrated in FIGS. 37 to 39 and other logic semiconductor integrated circuit devices of TTL levels 401, 402 . . . 40n, 501 to 505 and 600.

Referring to the figure, the outputs of the devices 401, 402 . . . 40n having the TTL level outputs are respectively supplied to the inputs IN₁, IN₂ . . . IN_(n) of the circuit IC, the outputs of which are supplied to the inputs of the devices 501, . . . 505 of TTL input levels.

Further, the output OUT₂ of the circuit IC and the output of the device 600 are connected in common, whereby both the devices IC and 600 execute a parallel operation.

Heat generated in large quantities in the input buffer 20 and output buffer 22 of the circuit IC can be dissipated to the ground line, power source line, input signal line and output signal line of the printed circuit board.

In addition, when the enable signal EN to be fed to the output buffer 22 is set at the low level, the outputs OUT₁, OUT₂ . . . OUT_(m) fall into the floating states, and the input levels of the devices 501, 502, 503 are set by the output level of the device 600.

Besides, a high speed is attained at the interface between the input buffer 20 and the devices 401, 402 . . . 40n; at the interface between the internal logic block 21 and the input buffer 20; at the interface between the output buffer 22 and the internal logic block 21; and at the interface between the devices 501 . . . 505 and the output buffer 20.

According to the foregoing embodiments, favorable effects can be achieved for reasons as stated below.

(1) Output transistors for executing the charge or discharge of the output capacitance C_(s) of an input level converter 201 are formed of bipolar transistors. Thus, the propagation delay times of the input level converter and the output capacitance-dependencies thereof can be lessened owing to the function that, even when smaller in device size than a MOS FET, the bipolar transistor exhibits a lower output resistance and a higher current gain, so it can produce a great charging current or discharging current.

(2) In the input level converter 201, a Schottky barrier diode for executing a majority carrier operation is connected between the base and collector of a bipolar transistor which is driven into its saturation region. Therefore, the injection of minority carriers from a collector layer into a base layer can be reduced, so that the storage time of the bipolar transistor can be shortened.

(3) In an input level converter 201 according to a preferred embodiment, the base signal or collector signal of a driver transistor Q₂ is transmitted to the base of a charging bipolar output transistor Q₃ through a MOS buffer which has a high input impedance and a voltage amplifying function. Thus, the operating speed of the output transistor Q₃ is enhanced owing to the high input impedance and the voltage amplifying function of the MOS buffer.

(4) In the input level converter 201 according to a preferred embodiment, a P-N-P emitter follower transistor Q₄ and a P-N junction diode D₂ are connected between an input terminal IN₁ and the driver transistor Q₂. Thus, the input threshold voltage of the input level converter 201 can be properly set. Moreover, since the input impedance of the P-N-P transistor Q₄ at the base thereof is enhanced owing to the current amplifying function thereof, the influence of the output impedance of a TTL level signal source connected to the input terminal IN₁ can be reduced.

(5) Output transistors for executing the charge or discharge of the output load capacitance C_(x) of an output level converter 221 are formed of bipolar transistors. Thus, the propagation delay times of the output level converter and the output capacitance-dependencies thereof can be lessened owing to the function that, even when smaller in device size than a MOS FET, the bipolar transistor exhibits a lower output resistance and a higher current gain, so it can produce a great charging current or discharging current.

(6) In the output level converter 221, a Schottky barrier diode for executing a majority carrier operation is connected between the base and collector of a bipolar transistor which is driven into its saturation region. Therefore, the injection of minority carriers from a collector layer into a base layer can be reduced, so that the storage time of the bipolar transistor can be shortened.

(7) In an output level converter 211 according to a preferred embodiment, a high input impedance MOS circuit is connected between the output of an internal logic block 21 and the base of a driver transistor Q₁₁. Thus, current to flow from the gate of the MOS FET of this MOS circuit to the output of the internal logic block 21 can be reduced down to a negligible level. Therefore, lowering in the integration density of the output circuit of the internal logic block 21 and lowering in the switching speed can be prevented.

(8) In the output level converter 221 according to a preferred embodiment, the high input impedance MOS circuit is endowed with the function of logically processing a plurality of output signals of the internal logic block 21. Thus, the design versatility of a logic semiconductor integrated circuit IC of the master slice type or the gate array type can be enhanced.

(9) In the output level converter 221 according to a preferred embodiment, a control circuit for controlling an output terminal OUT₁ into a floating state on the basis of an enable signal EN is arranged. Therefore, in a case where this output terminal OUT₁ and the output terminal of another logic circuit are connected in common, the level of the common output terminal can be set in accordance with the output of the other logic circuit.

(10) In a preferred embodiment, the internal logic block 21 which is formed of a pure CMOS circuit or a quasi-CMOS circuit thereby to have its power consumption reduced is arranged in the central part of the front surface of a semiconductor chip, while the input level converters 201, . . . and the output level converters 221, . . . each of which includes a plurality of bipolar transistors and exhibits a high power consumption are arranged in the peripheral edge parts of the front surface of the semiconductor chip. Thus, heat dissipation is facilitated. It has therefore been possible to put the logic semiconductor integrated circuit device IC into a radiation fin-less structure and to curtail the cost thereof.

(11) According to a preferred embodiment, the logic semiconductor integrated circuit device IC is put into a resin-molded structure, and hence, the curtailment of the cost thereof has become possible.

(12) Meanwhile, the input terminal IN₁ of the input level converter 201 is not connected to the gate of a MOS FET, but it is connected to the cathode of the Schottky barrier diode D₁ or the base of the P-N-P transistor Q₄. It has therefore been permitted to enhance the breakdown strength against a surge voltage applied to the input terminal IN₁.

While, in the above, the invention made by the inventiors has been concretely described in conjunction with the various illustrated embodiments, it is needless to say that the invention is not restricted to the foregoing embodiments but that it can be variously modified and altered within the scope of the claims without departing from the gist thereof.

For example, in FIG. 6, the arrangement can also be such that the level converters 201, 202 . . . 20n of the input buffer 20 execute ECL-CMOS level conversion, while the level converters 221, 222 . . . 22m of the output buffer 22 execute CMOS-ECL level conversion. It is needless to say that, to this end, the input buffer 20, internal logic block 21 and output buffer 22 may be operated with the ground level and a minus supply voltage -V_(EE). Likewise, in FIG. 6, the arrangement can be such that the level converters 201, 202 . . . 20n of the input buffer 20 execute i² L-CMOS level conversion, while the level converters 221, 222 . . . 22m of the output buffer 22 execute CMOS-i² L level conversion.

Further, in the embodiments of FIGS. 14 to 21, FIGS. 23 to 26 and FIGS. 29 and 30, the P-N-P emitter follower transistor Q₄ and the P-N junction diode D₂ in FIG. 31 may well be added.

In addition, the reason why the denominator L of the ratio W/L of the MOS FET is set at 3 is that the channel length of the MOS FET is assumed to be 3 μm. since that is a typical conventional value which is practically obtainable with present standard equipment. However, techniques are presently being developed which should ultimately permit channel length L to be fined to 2 μm, 1.5 μm and 1 μm or less owing to improvements in photolithography, and the denominator L of the ratio W/L will become smaller accordingly.

With the fining, the device sizes of bipolar transistors will be reduced more, and changes in the resistances of resistors within circuits will also become necessary.

The method of taking the large number of leads L₁, . . . L₆₄ out of the molding resin 301 is not restricted to the embodiment of FIG. 39, either. It is more appropriate for reducing the size of the lead frame L_(T) as well as the circuit device IC and attains a higher packaging density on the printed circuit board if the external shape of the molding resin 301 is made a substantially rectangular square, not an oblong, so as to take out the large number of leads L₁, . . . L₆₄ from all four sides.

While, in the above, the invention made by the inventors has been chiefly described for the cases of application to a logic semiconductor integrated circuit device, it is not restricted to these cases.

By way of example, it is needless to say that, not only the input buffer 20, internal logic block 21 and output buffer 22, but also any of a bipolar analog circuit, MOS analog circuit, P-channel MOS logic or N-channel MOS logic i² L circuit, and ECL circuit can be arranged on the semiconductor chip as may be needed. 

What is claimed is:
 1. A semiconductor integrated circuit comprising:(1) an input circuit having input and output terminals, said input circuit performing a switching operation responding to an input signal received at said input terminal and including means for providing an output signal at said output terminal, said means for providing the output signal in said input circuit including:a first bipolar transistor having a collector-emitter path coupled between a first potential terminal and said output terminal, and a base coupled to receive a base drive signal responding to said input signal, said first bipolar transistor executing one of a charge and discharge of a capacitance of said output terminal, switching means coupled between said output terminal and a second potential terminal and responsive to said input signal on said input terminal and for executing the other of said charge and said discharge of the capacitance, and a CMOS circuit having an input responding to said input signal and an output providing said base drive signal for said first bipolar transistor; and (2) an internal logic block including a plurality of gate circuits, said internal logic block preforming logic operations on input signals received at input terminals of said plurality of gate circuits and generating output signals based upon the logic operations at output terminals of said plurality of gate circuits, wherein said output terminal of said input circuit is commonly connected with input terminals of ones of said plurality of gate circuits in accordance with a predetermined gate array type arrangement, wherein the logic operations of said internal logic block is determined in accordance with the predetermined gate array type arrangement, and wherein said plurality of gate circuits of said internal logic block are formed in accordance with the predetermined gate array type arrangement to include a plurality of quasi-CMOS circuits and a plurality of CMOS circuits, input stages of said guasi-CMOS ciricuits being comprised of P-channel and N-channel MOSFETs and output stages of said quasi-CMOS circuits being comprised of bipolar transistors, each of said CMOS circuit including P-channel and N-channel MOSFETs.
 2. A semiconductor integrated circuit according to claim 1, wherein said internal logic block further comprises a flip-flop circuit which is constructed by combining first and second gate circuits, and output of said first gate circuit being connected to an input of said second gate circuit, an output of said second gate circuit being connected to an input of said first gate circuit, and each of said first and said second gate circuits being comprised of a quasi-CMOS circuit, an input stage of which is comprised of p-channel and n-channel MOSFETs and an output stage of which is comprised of bipolar output transistors.
 3. A semiconductor integrated circuit according to claim 2, wherein each of said first and said second gate circuits is a NAND gate circuit.
 4. A semiconductor integrated circuit according to claim 2, wherein each of said first and said second gate circuits is a NOR gate circuit.
 5. A semiconductor integrated circuit according to claim 1, wherein said internal logic block further comprises a combination of a first and a second gate circuit, an output of said first gate circuit being connected to an input of said second gate circuit and to an input of another circuit within said semiconductor integrated circuit, wherein said first gate circuit is comprised of a quasi-CMOS circuit, an input stage of which is comprises of p-channel and n-channel MOSFETs and an output stage of which is comprised of bipolar output transistors, and wherein at least an input stage of said second gate circuit is comprised of other p-channel and n-channel MOSFETs.
 6. A semiconductor integrated circuit according to claim 5, wherein said another circuit generates an output signal at an external output terminal of said semiconductor intergrated circuit.
 7. A semiconductor integrated circuit according to claim 5, wherein at least an output stage of said another circuit is comprised of bipolar output transistors.
 8. A semiconductor integrated circuit according to claim 1, wherein said switching means includes a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, and a base coupled to receive a signal responding to said input signal on said input terminal.
 9. A semiconductor integrated circuit according to claim 8, wherein said first and second bipolar transistors are of an NPN type.
 10. A semiconductor integrated circuit according to claim 1, wherein, in at least one of said quasi-CMOS circuits, said output stage thereof further comprises:a switching transistor having a current path coupled between said output terminal and said second potential terminal, the current path being coupled in series to an emitter-collector path of said bipolar transistor in said output stage thereof between said first and second potential terminals, wherein, in said input stage of said at least one quasi-CMOS circuit, said P-channel MOSFET has a source-drain path coupled between said first potential terminal and the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, said N-channel MOSFET has a source-drain path coupled to the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, and wherein a control terminal of said switching transistor responds to a signal reversed in phase from a signal appearing at the base of said bipolar transistor in said output stage in said at least one quasi-CMOS circuit.
 11. A semiconductor integrated circuit according to claim 10, wherein said switching transistor includes a third bipolar transistor, the control terminal and the current path of said switching transistor corresponding to a base and an emitter-collector path of said third bipolar transistor,wherein said at least one quasi-CMOS circuit includes a first resistance element coupled between said base of said bipolar transistor and a drain of said N-channel MOSFET, and a second resistance element coupled between said base of said third bipolar transistor and said second potential terminal, and wherein, in said at least one quasi-CMOS circuit, a source and a drain of said N-channel MOSFET are coupled to the base and a collector of said third bipolar transistor, repectively.
 12. A semiconductor integrated circuit according to claim 11, wherein said at least one quasi-CMOS circuit further includes:another input terminal; another P-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said first potential terminal and said base of said bipolar transistor; and another N-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said base and collector of said third bipolar transistor, and wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 13. A semiconductor integrated circuit according to claim 1, wherein said bipolar transistors in said output stage of at least one of said quasi-CMOS circuits include:a first bipolar transistor having an emitter-collector path coupled between said first potential terminal and said output terminal, and a base; and a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, wherein said input stage of said at least one quasi-CMOS circuit includes:said P-channel MOSFETs having their source-drain paths coupled between said first potential terminal and the base of said first bipolar transistor, and their gates coupled to respective ones of said input terminals; said N-channel MOSFETs having their source-drain paths coupled between said output terminal and the base of said second bipolar transistor, and their gates coupled to respective ones of said input terminals, wherein said source-drain paths of one said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETS are coupled in series to one another.
 14. A semiconductor integrated circuit according to claim 13, wherein said at least one quasi-CMOS circuit further includes:a first resistor element coupled to the base of said first bipolar transistor and said output terminals; and a second resistor element coupled between the base of said second bipolar transistor and said second potential terminal.
 15. A semiconductor integrated circuit according to claim 14, wherein said first resistor element is coupled between the base of said first bipolar transistor and said output terminal.
 16. A semiconductor integrated circuit comprising:(1) an internal logic block including a plurality of gate circuits, said internal logic block performing logic operations on input signals received at input terminals of said plurality of gate circuits and generating output signals based upon the logic operations at output terminals of said plurality of gate circuits, wherein the logic operations of the internal logic block are determined in accordance with a predetermined gate array type arrangement, and wherein ones of said plurality of gate circuits of said internal logic block are formed in accordance with the predetermined gate array type arrangement to be comprised of quasi-CMOS circuits, input stages of which are comprised of p-channel and n-channel MOSFETs and output stages of which are comprised of bipolar transistor; and (2) an output circuit having input and output terminals, said output circuit performing a switching operation responding to an input signal received at said input terminal of said output circuit and including means for providing an output signal at said output terminal of said output circuit, wherein at least one of said output terminals of said plurality of gate circuits is coupled to said input terminal of said output circuit in accordance with the predetermined gate array type arrangement, wherein said means for providing the output signal in said output circuit includes a bipolar output transistor, a base of which responds to said input signal received at said input terminal of said output circuit, a current flowing through a collector-emitter path of said bipolar output transistor charging or discharging a load capacitance at said output terminal of said output circuit, and wherein said output circuit further includes a MOS circuit which is coupled between the base of said bipolar output transistor and one of said output terminals of said internal logic block.
 17. A semiconductor integrated circuit according to claim 16, wherein said output terminal of said output circuit is coupled to an external terminal of said semiconductor integrated circuit.
 18. A semiconductor integrated circuit according to claim 16, wherein said bipolar transistors and said bipolar output transistors are of an NPN type.
 19. A semiconductor integrated circuit according to claim 16, wherein said internal logic block is arranged in a central part of a semiconductor chip, and wherein said output circuit is arranged at a periphery of said semiconductor chip.
 20. A semiconductor integrated circuit according to claim 16, wherein said output circuit includes a plurality of input terminals coupled to receive a plurality of output signals of said internal logic block, wherein said MOS circuit is connected between said base of said bipolar output transistor and a plurality of output terminals of said internal logic block, and wherein said MOS circuit includes means for logically processing said plurality of output signals of said internal logic block.
 21. A semiconductor integrated circuit according to claim 16, wherein said output circuit includes a Schottky barrier diode coupled between said base and said collector of said bipolar output transistor.
 22. A semiconductor integrated circuit according to claim 16, wherein, in at least one of said quasi-CMOS circuits, said output stage thereof further comprises:a switching transistor having a current path coupled between said output terminal and said second potential terminal, the current path being coupled in series to an emitter-collector path of said bipolar transistor in said output stage thereof between said first and second potential terminals, wherein, in said input stage of said at least one quasi-CMOS circuit, said P-channel MOSFET has a source-drain path coupled between said first potential terminal and the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, said N-channel MOSFET has a source-drain path coupled to the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, and wherein a control terminal of said switching transistor responds to a signal reversed in phase from a signal appearing at the base of said bipolar transistor in said output stage in said at least one quasi-CMOS circuit.
 23. A semiconductor integrated circuit according to claim 22, wherein said switching transistor includes a second bipolar transistor, the control terminal and the current path of said switching transistor corresponding to a base and an emitter-collector path of said second bipolar transistor,wherein said at least one quasi-CMOS circuit includes a first resistance element coupled between said base of said bipolar transistor and a drain of said N-channel MOSFET, and a second resistance element coupled between said base of said second bipolar transistor and said second potential terminal, and wherein, in said at least one quasi-CMOS circuit, a source and a drain of said N-channel MOSFET are coupled to the base and a collector of said second bipolar transistor, respectively.
 24. A semiconductor integrated circuit according to claim 23, wherein said at least one quasi-CMOS circuit further includes:another input terminal; another P-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said first potential terminal and said base of said bipolar transistor; and another N-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said base and collector of said second bipolar transistor, and wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 25. A semiconductor integrated circuit according to claim 16, wherein said bipolar transistors in said output stage of at least one of said quasi-CMOS circuits include:a first bipolar transistor having an emitter-collector path coupled between said first potential terminal and said output terminal, and a base; and a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, wherein said input stage of said at least one quasi-CMOS circuit includes:said P-channel MOSFETs having their source-drain paths coupled between said first potential terminal and the base of said first bipolar transistor, and their gates coupled to respective ones of said input terminals; said N-channel MOSFETs having their source-drain paths coupled between said output terminal and the base of said second bipolar transistor, and their gates coupled to respective ones of said input terminals, wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 26. A semiconductor integrated circuit according to claim 25, wherein said at least one quasi-CMOS circuit further includes:a first resistor element coupled to the base of said first bipolar transistor and said output terminal; and a second resistor element coupled between the base of said second bipolar transistor and said second potential terminal.
 27. A semiconductor integrated circuit according to claim 26, wherein said first resistor element is coupled between the base of said first bipolar transistor and said output terminal.
 28. A semiconductor integrated circuit comprising:(1) a plurality of input circuits, each of said input circuits having input and output terminals, performing a switching operation responding to an input signal received at said input terminal and including means for providing an output signal at said output terminal, said means for providing the output signal in one of said plurality of input circuits including:a first bipolar transistor having a collector-emitter path coupled between a first potential terminal and said output terminal, and a base coupled to receive a base drive signal responding to said input signal, said first bipolar transistor executing one of a charge and a discharge of a capacitance of said output terminal, switching means coupled between said output terminal and a second potential terminal and responsive to said input signal on said input terminal and for executing the other of said charge and said discharge of the capacitance, and a CMOS circuit having an input responding to said input signal and an output providing said base drive signal for said first bipolar transistor; and (2) an internal logic block including a plurality of gate circuits, said internal logic block performing logic operations on input signals received at input terminals of said plurality of gate circuits and generating output signals based upon the logic operations at output terminals of said plurality of gate circuits, wherein the logic operations of the internal logic block are determined in accordance with a predetermined gate array type arrangement, wherein the output terminal of said one of said plurality of input circuits is connected with a predetermined plurality of said input terminals of said plurality of gate circuits in accordance with the predetermined gate array type arrangement, and wherein said plurality of gate circuits of said internal logic block are formed in accordance with the predetermined gate array type arrangement so as to be comprised of quasi-CMOS circuits, the input stages of which are comprised of p-channel and n-channel MOSFETs and the output stages of which are comprised of bipolar transistors.
 29. A semiconductor integrated circuit according to claim 28, wherein said switching means includes a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, and a base coupled to receive a signal responding to said input signal on said input terminal.
 30. A semiconductor integrated circuit according to claim 28, wherein said first and second bipolar transistors are of an NPN type.
 31. A semiconductor integrated circuit according to claim 28, wherein said internal logic block is arranged in a central part of a semiconductor chip, and wherein said input circuits are arranged at a periphery of said semiconductor chip.
 32. A semiconductor integrated circuit according to claim 28, wherein, in at least one of said quasi-CMOS circuits, said output stage thereof further comprises:a switching transistor having a current path coupled between said output terminal and said second potential terminal, the current path being coupled in series to an emitter-collector path of said bipolar transistor in said output stage thereof between said first and second potential terminals, wherein, in said input stage of said at least one quasi-CMOS circuit, said P-channel MOSFET has a source-drain path coupled between said first potential terminal and the base of said bipolar transistor of said at least on quasi-CMOS circuit, and a gate coupled to said input terminal, said N-channel MOSFET has a source-drain path coupled to the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, and wherein a control terminal of said switching transistor responds to a signal reversed in phase from a signal appearing at the base of said bipolar transistor in said output stage in said at least one quasi-CMOS circuit.
 33. A semiconductor integrated circuit according to claim 32, wherein said switching transistor includes a third bipolar transistor, the control terminal and the current path of said switching transistor corresponding to a base and an emitter-collector path of said third bipolar transistor,wherein said at least one quasi-CMOS circuit includes a first resistance element coupled between said base of said bipolar transistor and a drain of said N-channel MOSFET, and a second resistance element coupled between said base of said third bipolar transistor and said second potential terminal, and wherein, in said at least one quasi-CMOS circuit, a source and a drain of said N-channel MOSFET are coupled to the base and a collector of said third bipolar transistor, respectively.
 34. A semiconductor integrated circuit according to claim 33, wherein said at least one quasi-CMOS circuit further includes:another input terminal; another P-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said first potential terminal and said base of said bipolar transistor; and another N-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said base and collector of said third bipolar transistor, and wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETS are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETS and said N-channel MOSFETs are coupled in series to one another.
 35. A semiconductor integrated circuit according to claim 28, wherein said bipolar transistors in said output stage of at least one of said quasi-CMOS circuits include:a first bipolar transistor having an emitter-collector path coupled between said first potential terminal and said output terminal, and a base; and a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, wherein said input stage of said at least one quasi-CMOS circuit includes:said P-channel MOSFETs having their source-drain paths coupled between said first potential terminal and the base of said first bipolar transistor, and their gates coupled to respective ones of said input terminals; said N-channel MOSFETs having their source-drain paths coupled between said output terminal and the base of said second bipolar transistor, and their gates coupled to respective ones of said input terminals, wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 36. A semiconductor integrated circuit according to claim 35, wherein said at least one quasi-CMOS circuit further includes:a first resistor element coupled to the base of said first bipolar transistor and said output terminal; and a second resistor element coupled between the base of said second bipolar transistor and said second potential terminal.
 37. A semiconductor integrated circuit according to claim 36, wherein said first resistor element is coupled between the base of said first bipolar transistor and said output terminal.
 38. A semiconductor integrated circuit comprising:(1) an input circuit having input and output terminals, said input circuit performing a switching operation responding to an input signal received at said input terminal and including means for providing an output signal at said output terminal, said means for providing the output signal in said input circuit including:a first bipolar transistor having a collector-emitter path coupled between a first potential terminal and said output terminal, and a base coupled to receive a base drive signal responding to said input signal, said first bipolar transistor executing one of a charge and a discharge of a capacitance of said output terminal, switching means coupled between said output terminal and a second potential terminal and responsive to said input signal on said input terminal and for executing the other of said charge and said discharge of the capacitance, and a drive circuit having an input responding to said input signal and an output providing said base drive signal for said first bipolar transistor, and including P-channel and N-channel MOSFETs; and (2) an internal logic block including a plurality of gate circuits, said internal logic block performing logic operations on input signals received at input terminals of said plurality of gate circuits and generating output signals based upon the logic operations at output terminals of said plurality of gate circuits, wherein said output terminal of said input circuit is commonly connected with input terminals of ones of said plurality of gate circuits in accordance with a predetermined gate array type arrangement, wherein the logic operations of said internal logic block is determined in accordance with the predetermined gate array type arrangement, and wherein said plurality of gate circuits of said internal logic block are formed in accordance with the predetermined gate array type arrangement to include a plurality of quasi-CMOS circuits and a plurality of CMOS circuits, input stages of said quasi-CMOS circuits being comprised of P-channel and N-channel MOSFETs and output stages of said quasi-CMOS circuits being comprised of bipolar transistors, each of said CMOS circuits including P-channel and N-channel MOSFETs.
 39. A semiconductor integrated circuit according to claim 38, wherein said internal logic block further comprises a flip-flop circuit which is constructed by combining first and second gate circuits, and output of said first gate circuit being connected to an input of said second gate circuit, an output of said second gate circuit being connected to an input of said first gate circuit, and each of said first and said second gate circuits being comprised of a quasi-CMOS circuit, an input stage of which is comprised of p-channel and n-channel MOSFETs and an output stage of which is comprised of bipolar output transistors.
 40. A semiconductor integrated circuit according to claim 39, wherein each of said first and said second gate circuits is a NAND gate circuit.
 41. A semiconductor integrated circuit according to claim 39, wherein each of said first and said second gate circuits is a NOR gate circuit.
 42. A semiconductor integrated circuit according to claim 38, wherein said internal logic block further comprises a combination of a first and a second gate circuit, an output of said first gate circuit being connected to an input of said second gate circuit and to an input of another circuit within said semiconductor integrated circuit, wherein said first gate circuit is comprised of a quasi-CMOS circuit, an input stage of which is comprised of p-channel and n-channel MOSFETs and an output stage of which is comprised of bipolar output transistors, and wherein at least an input stage of said second gate circuit is comprised of other p-channel and n-channel MOSFETs.
 43. A semiconductor integrated circuit according to claim 42, wherein said another circuit generates an output signal at an external output terminal of said semiconductor integrated circuit.
 44. A semiconductor integrated circuit according to claim 42, wherein at least an output stage of said another circuit is comprised of bipolar output transistors.
 45. A semiconductor integrated circuit according to claim 38, wherein, in at least one of said quasi-CMOS circuits, said output stage thereof further comprises:a switching transistor having a current path coupled between said output terminal and said second potential terminal, the current path being coupled in series to an emitter-collector path of said bipolar transistor in said output stage thereof between said first and second potential terminals, wherein, in said input stage of said at least one quasi-CMOS circuit, said P-channel MOSFET has a source-drain path coupled between said first potential terminal and the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, said N-channel MOSFET has a source-drain path coupled to the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, and wherein a control terminal of said switching transistor responds to a signal reversed in phase from a signal appearing at the base of said bipolar transistor in said output stage in said at least one quasi-CMOS circuit.
 46. A semiconductor integrated circuit according to claim 45, wherein said switching transistor includes a third bipolar transistor, the control terminal and the current path of said switching transistor corresponding to a base and an emitter-collector path of said third bipolar transistor,wherein said at least one quasi-CMOS circuit includes a first resistance element coupled between said base of said bipolar transistor and a drain of said N-channel MOSFET, and a second resistance element coupled between said base of said third bipolar transistor and said second potential terminal, and wherein, in said at least one quasi-CMOS circuit, a source and a drain of said N-channel MOSFET are coupled to the base and a collector of said third bipolar transistor, respectively.
 47. A semiconductor integrated circuit according to claim 46, wherein said at least one quasi-CMOS circuit further includes:another input terminal; another P-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said first potential terminal and said base of said bipolar transistor; and another N-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said base and collector of said third bipolar transistor, and wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETS and said N-channel MOSFETs are coupled in series to one another.
 48. A semiconductor integrated circuit according to claim 38, wherein said bipolar transistors in said output stage of at least one of said quasi-CMOS circuits include:a first bipolar transistor having an emitter-collector path coupled between said first potential terminal and said output terminal, and a base; and a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, wherein said input stage of said at least one quasi-CMOS circuit includes:said P-channel MOSFETs having their source-drain paths coupled between said first potential terminal and the base of said first bipolar transistor, and their gates coupled to respective ones of said input terminals; said N-channel MOSFETs having their source-drain paths coupled between said output terminal and the base of said second bipolar transistor, and their gates coupled to respective ones of said input terminals, wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 49. A semiconductor integrated circuit according to claim 48, wherein said at least one quasi-CMOS circuit further includes:a first resistor element coupled to the base of said first bipolar transistor and said output terminal; and a second resistor element coupled between the base of said second bipolar transistor and said second potential terminal.
 50. A semiconductor integrated circuit according to claim 49, wherein said first resistor element is coupled between the base of said first bipolar transistor and said output terminal.
 51. A semiconductor integrated circuit according to claim 38, wherein said switching means includes a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, and a base coupled to receive a signal responding to said input signal on said input terminal.
 52. A semiconductor integrated circuit according to claim 51, wherein said first and second bipolar transistors are of an NPN type.
 53. A semiconductor integrated circuit comprising:(1) a plurality of input circuits, each of said input circuits having input and output terminals, performing a switching operation responding to an input signal received at said input terminal and including means for providing an output signal at said output terminal, and said means for providing the output signal in one of said plurality of input circuits including:a first bipolar transistor having a collector-emitter path coupled between a first potential terminal and said output terminal, and a base coupled to receive a base drive signal responding to said input signal, and first bipolar transistor executing one of a charge and a discharge of a capacitance of said output terminal, switching means coupled between said output terminal and a second potential terminal and responsive to said input signal on said input terminal and for executing the other of said charge and said discharge of the capacitance, and a drive circuit having an input responding to said input signal and an output providing said base drive signal for said first bipolar transistor, and including P-channel and N-channel MOSFETs; and (2) an internal logic block including a plurality of gate circuits, and internal logic block performing logic operations on input signals received at input terminals of said plurality of gate circuits and generating output signals based upon the logic operations at output terminals of said plurality of gate circuits, wherein the logic operations of the internal logic block are determined in accordance with a predetermined gate array type arrangement, wherein the output terminal of said one of said plurality of input circuits is connected with a predetermined plurality of said input terminals of said plurality of gate circuits in accordance with the predetermined gate array type arrangement, and wherein said plurality of gate circuits of said internal logic block are formed in accordance with the predetermined gate array type arrangement so as to be comprised of quasi-CMOS circuits, the input stages of which are comprised of p-channel and n-channel MOSFETs and the output stages of which are comprised of bipolar transistors.
 54. A semiconductor integrated circuit according to claim 53, wherein said switching means includes a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, and a base coupled to receive a signal responding to said input signal on said input terminal.
 55. A semiconductor integrated circuit according to claim 54, wherein said first and second bipolar transistors are of an NPN type.
 56. A semiconductor integrated circuit according to claim 53, wherein said internal logic block is arranged in a central part of a semiconductor chip, and wherein said input circuits are arranged at a periphery of said semiconductor chip.
 57. A semiconductor integrated circuit according to claim 53, wherein, in at least one of said quasi-CMOS circuits, said output stage thereof further comprises:a switching transistor having a current path coupled between said output terminal and said second potential terminal, the current path being coupled in series to an emitter-collector path of said bipolar transistor in said output stage thereof between said first and second potential terminals, wherein, in said input stage of said at least one quasi-CMOS circuit, said P-channel MOSFET has a source-drain path coupled between said first potential terminal and the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, said N-channel MOSFET has a source-drain path coupled to the base of said bipolar transistor of said at least one quasi-CMOS circuit, and a gate coupled to said input terminal, and wherein a control terminal of said switching transistor responds to a signal reversed in phase from a signal appearing at the base of said bipolar transistor in said output stage in said at least one quasi-CMOS circuit.
 58. A semiconductor integrated circuit according to claim 57, wherein said switching transistor includes a third bipolar transistor, the control terminal and the current path of said switching transistor corresponding to a base and an emitter-collector path of said third bipolar transistor,wherein said at least one quasi-CMOS circuit includes a first resistance element coupled between said base of said bipolar transistor and a drain of said N-channel MOSFET, and a second resistance element coupled between said base of said third bipolar transistor and said second potential terminal, and wherein, in said at least one quasi-CMOS circuit, a source and a drain of said N-channel MOSFET are coupled to the base and a collector of said third bipolar transistor, respectively.
 59. A semiconductor integrated circuit according to claim 58, wherein said at least one quasi-CMOS circuit further includes:another input terminal; another P-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said first potential terminal and said base of said bipolar transistor; and another N-channel MOSFET having a gate coupled to said another input terminal, and a source-drain path coupled between said base and collector of said third bipolar transistor, and wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 60. A semiconductor integrated circuit according to claim 53, wherein said bipolar transistors in said output stage of at least one of said quasi-CMOS circuits include:a first bipolar transistor having an emitter-collector path coupled between said first potential terminal and said output terminal, and a base; and a second bipolar transistor having an emitter-collector path coupled between said output terminal and said second potential terminal, wherein said input stage of said at least one quasi-CMOS circuit includes:said P-channel MOSFETS having their source-drain paths coupled between said first potential terminal and the base of said first bipolar transistor, and their gates coupled to respective ones of said input terminals; said N-channel MOSFETs having their source-drain paths coupled between said output terminal and the base of said second bipolar transistor, and their gates coupled to respective ones of said input terminals, wherein said source-drain paths of one of said P-channel MOSFETs and said N-channel MOSFETs are coupled in parallel to one another while said source-drain paths of the other of said P-channel MOSFETs and said N-channel MOSFETs are coupled in series to one another.
 61. A semiconductor integrated circuit according to claim 60, wherein said at least one quasi-CMOS circuit further includes:a first resistor element coupled to the base of said first bipolar transistor and said output terminal; and a second resistor element coupled between the base of said second bipolar transistor and said second potential terminal.
 62. A semiconductor integrated circuit according to claim 61, wherein said first resistor element is coupled between the base of said first bipolar transistor and said output terminal. 